Top 3 Itco Solutions Jobs

Hardware Design Engineer
ITCO Solutions —San Jose, CA
- $100,000 - $200,000 a year
- Full-time
- Hybrid work
- Analysis skills
- Senior level
- Electrical Engineering
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8d
Oracle EBS Developer
ITCO Solutions —Marlborough, MA
- $80,000 - $172,000 a year
- Full-time
- Computer Science
- Bachelor's degree
- In-person
- Dental insurance
- Tuition reimbursement
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3d
GCP Architect
ITCO Solutions —Salt Lake City, UT
- $60 - $75 an hour
- Contract
- 8 years
- US work authorization
- In-person
Quick Apply
3d

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Oracle EBS OAF Developer
CGI Group, Inc. —Marlborough, MA
Education: Bachelor's degree in computer science or related field. . Design, develop, and maintain Oracle EBS OAF customizations, extensions, and enhancements.
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Oracle EBS Developer
Blue Rose Consulting Group, Inc. —Remote
Collaborate with functional and technical teams to gather requirements and translate business needs into technical solutions. Full-time (40 hours/week).
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Hardware Design Engineer

ITCO Solutions -
San Jose, CA

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Job Details

Full-time | Contract
$100,000 - $200,000 a year
8 days ago

Qualifications

Engineering development testing
Tooling
Electronics design
Digital circuit design
Computer hardware

Full Job Description

YOUR IMPACT
You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will develop timing constrains at both block level and full-chip and validate them using industry standard timing constraints verification tools such as TCM, Timevision. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you’ll contribute to developing next-generation networking chips.

Being a member of design team who develops block level and full-chip SDCs and works with physical design and DFT teams to close full-chip timing in multiple timing modes.
You will work design and architecture teams in understanding clocking structure, develop timing constraints and validate them though constraints verification tool before releasing them for physical design.
Option to also do block level RTL design or block or top-level IP integration.
Helping develop efficient methodology to promote block level SDCs to full-chip, and to push down full-chip SDCs to block level.
Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
Reviewing block level SDCs and clocking diagrams and collaborate with RTL design owners on SDC development.
Contribute to full-chip clocking design including diagrams and related documentation.

Minimum Qualifications:

Bachelor’s Degree in Electrical or Computer Engineering with 6+ years of ASIC or related experience or Master’s Degree in Electrical or Computer Engineering with 4+ years of ASIC or related experience.
Experience with synthesis tools (e.g.. Client DC/DCG/FC), STA tools such as Primetime and must have knowledge of HDL such as Verilog/SystemVerilog programming, and scripting languages such as Shell, Perl, and must have strong experience scripting with TCL.
Experience with digital design concepts (e.g.. clocking, timing exceptions and async boundaries).
Experience with block/full chip SDC development in functional and test modes.
Experience with microarchitecture and RTL implementation.

Pay: $100,000.00 - $200,000.00 per year

Experience:

SDC: 4 years (Required)
PrimeTime: 4 years (Required)
ASIC: 3 years (Required)

Ability to Commute:

San Jose, CA 95134 (Required)

Ability to Relocate:

San Jose, CA 95134: Relocate before starting work (Required)

Work Location: Hybrid remote in San Jose, CA 95134

Quick Apply

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