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  • Asic/SOC/System Verilog/Perl
    Systems Pros - Washington, DC
    5-10 years Design Verification Experience Design Verification System Verilog HVL Perl C++ Test Benches RTL SOC Linux ARM
    from Net-Temps
  • ASIC Verification Engineer Specman / SystemVerilog
    Formalized Design - Houston, TX
    Must have BOTH Specman and SystemVerilog experience. * 5+ years C and DSP assembly Design verification ... Must know VHDL or Verilog language and using synthesis tools...
    from Dice
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  • Asic/SOC/System Verilog/Perl
    Systems Pros - Billerica, MA
    Design Verification System Verilog HVL Perl C++ Test Benches RTL SOC Linux ARM 5-10 Years Design Verification Experience
    from Dice
  • ASIC Verification
    Asicsoft - San Jose, CA
    Develop test benches and test cases; strong debug skills Must have experience with at least one: - System Verilog (preferred), SystemC, E or Vera -strong scripting skills Please...
    from Dice
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