Top 1944 ASIC design Jobs

Lead ASIC DFT Engineer
Cyient —San Jose, CA
- $80 - $85 an hour
- Full-time
- Analysis skills
- Mentoring
- In-person
Quick Apply
Lead ASIC DFT Engineer
Cyient —Remote
- From $100 an hour
- Full-time
- Remote
- Analysis skills
- Mentoring
- Senior level
Quick Apply
Analog Design Manager
elix sourcing solutions —Cork, PA
- $100,000 - $140,000 a year
- Senior level
- Leadership
5d
FPGA Design/Verification Engineer
The Structures Company, LLC —Littleton, CO
- $80 - $100 an hour
- Contract
- Computer Science
- Mid-level
- 3 years
- Health insurance
- Dental insurance
Quick Apply
Principal Physical Design Engineering Lead ($400-500k)
Everforth —Fort Collins, CO
- Up to $230,000 a year
- Full-time
- No experience needed
- US work authorization
- Scripting
- Health savings account
- Employee stock purchase plan
8d
ASIC Design Engineer
Career Finders —San Diego, CA
- Mid-level
- Analysis skills
- Electrical Engineering
ASIC Design Verification Engineer
Positron AI —Remote
- $200,000 - $350,000 a year
- Full-time
- Remote
- Master's degree
- 8 years
- Analysis skills
Quick Apply
ASIC Verification Engineer (Remote)
ASIC North, Inc. —Remote
- $120,000 - $165,000 a year
- Full-time
- Remote
- Bachelor of Science
- Travel
- Senior level
- Wellness program
- Health savings account
14d
ASIC Hardware Design Engineer - New College Grad 2026
NVIDIA —Austin, TX
- $116,000 - $218,500 a year
- Full-time
- Master's degree
- Analysis skills
- Software development
DFT Design Engineer
Cadence Design Systems —Austin, TX
- Full-time
- Mid-level
- Analysis skills
- 2 years
Jr. ASIC Design Engineer
Fermilab —Batavia, IL
- $70,800 - $93,200 a year
- Full-time
- Hybrid work
- Background check
- Engineering
- Pass drug screening
- Disability insurance
- Health insurance
Design for Test Engineer - Early Career
Marvell —Westborough, MA
- $108,500 - $160,510 a year
- Full-time
- Data analysis skills
- Master's degree
- Analysis skills
- Employee stock purchase plan
Digital IC Design Engineer
Microelectronics Research Development Corporation —Colorado
- Mid-level
- C++
- Doctor of Philosophy
ASIC Design Verification Engineer
K2 Space —Remote
- $130,000 - $200,000 a year
- Remote
- Bachelor of Science
- 3 years
- Senior level
- Paid parental leave
- Health insurance
13d
New Graduate Engineer, ASIC Design (Starshield)
SpaceX —Hawthorne, CA
- $125,000 - $150,000 a year
- Weekends as needed
- Computer Science
- Master's degree
- Travel
- Paid parental leave
- Employee stock purchase plan
ASIC Design Engineer
Sivaltech —Milpitas, CA
- Mid-level
- Bachelor's degree
ASIC Design Engineer
Broadcom —Irvine, CA
- $108,000 - $172,800 a year
- Full-time
- 6 years
- Master's degree
- Fair chance
- Employee stock purchase plan
- Paid holidays
ASIC Design Verification Engineer
Broadcom —Irvine, CA
- $129,400 - $207,000 a year
- Full-time
- 3 years
- Master's degree
- Bachelor's degree
- Employee stock purchase plan
- Paid holidays
ASIC Verification Engineer - New College Grad 2026
NVIDIA —Austin, TX
- $100,000 - $189,750 a year
- Full-time
- Computer science
- Computer Science
- Bachelor of Science
Staff Hardware Design Engineer
Tensordyne —Sunnyvale, CA
- Remote
- 7 years
- Bachelor of Science
- Manufacturing
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Lead ASIC DFT Engineer

Cyient -
San Jose, CA

Quick Apply

Job Details

Full-time | Contract
$80 - $85 an hour

Qualifications

Analog circuit design
Engineering development testing
Electronics functional testing
Integrated circuits (ICs)
Ramps
Analysis skills
SoC
System architecture design
Simulation tools
Root cause analysis
Test analysis
Python
Debugging
Cross-functional communication

Full Job Description

Title - Lead ASIC DFT Engineer

Location – San Jose, CA.

Duration - Contract

Job Description

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
Act as a technical escalation point for advanced DFT and post-silicon debug issues.
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

Strong hands-on experience in ASIC DFT with end-to-end ownership.
Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
Experience with MBIST implementation and verification; SMS experience preferred.
Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
Proven post-silicon debug and silicon bring-up experience.
Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

MBIST post-silicon validation.
ATPG simulations and fault coverage debug.
DFT RTL, DFD, DFT verification, and IP-level DFT integration.
DFT SDC creation and DFT timing closure support.
Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
TCL/PERL scripting for DFT automation, reporting, and debug.
Experience working across multiple ASIC technology nodes and complex product development cycles.
Familiarity with yield learning, diagnosis, and manufacturing test optimization.

Pay: $80.00 - $85.00 per hour

Work Location: In person

Quick Apply

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