Top 279 Asic Design Manager Jobs

ASIC Digital Physical Design Manager
Keysight Technologies, Inc. —Colorado Springs, CO
- $151,000 - $253,000 a year
- Full-time
- 5 years
- Bachelor of Science
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ASIC Program Manager
BrainChip, Inc. —Laguna Hills, CA
- Contract
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- 7 years
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Senior Principal Engineer Digital ASIC Design/Manager
Tubis Technology, Inc. —San Diego, CA
- $214,000 - $348,000 a year
- Online Application
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FPGA Design Manager / Section Lead
BAE Systems Inc. —Totowa, NJ
- $153,377 - $260,743 a year
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- Microsoft Word
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- Master's degree
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Sr Principal ASIC FPGA Engineer (Sign-on Bonus Available)
General Dynamics Mission Systems, Inc —Scottsdale, AZ
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- 8 years
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Senior Principal ASIC FPGA Engineer
General Dynamics Mission Systems, Inc —Boise, ID
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Analog Design Manager
elix sourcing solutions —Cork, PA
- $100,000 - $140,000 a year
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Systems Engineering Manager 2 (SIT&E)
Northrop Grumman —Baltimore, MD
- $153,800 - $230,800 a year
- Overtime
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- Doctor of Philosophy
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14d
Principal Electrical Engineer-FPGA Design- Onsite Tucson, AZ
Raytheon —Tucson, AZ
- $107,500 - $204,500 a year
- Full-time
- 8 years
- In-person
- Senior level
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Lead Program Management
L3Harris Technologies —Camden, NJ
- $125,000 - $232,000 a year
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- 7 years
- Microsoft Access
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9d
Electrical Engineering Manager (FPGA)
Three Point Solutions, Inc. —Rochester, NY
- $120,000 - $150,000 a year
- Full-time
- 8 years
- Bachelor's degree
- Mentoring
- Health savings account
- Relocation assistance
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7d
Principal Technical Program Manager – FEIC ASIC Development – TeraWave
Blue Origin —San Francisco Bay Area, CA
- $249,235.00 - $348,928.65 a year
- Full-time
- Background check
- DOT physical examination
- Fair chance
- Paid parental leave
- Paid holidays
Analog Design Engineering Manager
Intel —Phoenix, AZ
- $220,920 - $311,890 a year
- Full-time
- Office
- Master's degree
- 8 years
- Health insurance
Digital ASIC Design Manager
Keysight Technologies, Inc. —Colorado Springs, CO
- $151,000 - $253,000 a year
- Full-time
- Bachelor of Science
- Mentoring
- Recruiting
- Health savings account
- Employee stock purchase plan
Analog IP Design Execution Manager
Intel —Phoenix, AZ
- $190,610 - $269,100 a year
- Full-time
- Management
- 5 years
- Office
- Health insurance
Sr. Engineer, ASIC Design
Ayar Labs —San Jose, CA
- $160,000 - $192,000 a year
- Bachelor of Science
- Writing skills
- Mid-level
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Security Engineering Manager, AWS Foundational & Hardware Security
Amazon.com Services LLC —Remote
- $175,100 - $236,900 a year
- Full-time
- Computer Science
- 3 years
- Master's degree
- AD&D insurance
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ASIC and Logic Design Engineering Manager
Teradyne —North Reading, MA
- $155,500 - $248,700 a year
- Full-time
- 5 years
- Master's degree
- Analysis skills
- Paid holidays
- Disability insurance
ASIC Technical Program Manager
Etched —San Jose, CA
- Full-time
- Computer Science
- 5 years
- Engineering
- Health insurance
- Dental insurance
Senior Engineer, Physical Design (ASIC/SoC Place & Route) (Austin, TX)(5560)
TSMC —Austin, TX
- $106,500 - $162,000 a year
- Hybrid work
- 7 years
- Computer Science
- Office

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ASIC Digital Physical Design Manager

Keysight Technologies, Inc. -
Colorado Springs, CO

Apply Now

Job Details

Full-time
$151,000 - $253,000 a year

Benefits

Health savings account
Employee stock purchase plan
Paid holidays
Disability insurance
Health insurance
Dental insurance
401(k)
Flexible spending account
Tuition reimbursement
Adoption assistance
Family leave
Vision insurance

Qualifications

Project development phase management
Integrated circuits (ICs)
Design engineering
Project risk management

Full Job Description

Overview:

Keysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.

Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.

This role sits within Keysight Laboratories—a globally recognized technology organization that enables Keysight to be first to market with breakthrough, highly differentiated solutions. Our team of senior engineers has delivered generations of innovation across ASIC and product development, spanning the breadth of the technology landscape. You’ll join a high-performance, globally connected engineering organization designing and delivering next-generation Digital and Mixed signal ASICs.

A sustained driver of Keysight’s success is the creation and deployment of breakthrough digital and mixed-signal ASICs that unlock step-function performance and customer value in new products. We are seeking an ASIC Physical Design R&D Manager to lead our ASIC Physical Design team—overseeing end-to-end physical implementation and ensuring designs meet aggressive performance, power, and area targets through tapeout and into product development.

The position is based in Colorado Springs at the foot of Pikes Peak, with a purpose-built development campus that brings engineering, advanced technology development, assembly, and machining together in one location. Outside the lab, the campus supports an active lifestyle with on-site fitness and recreation, and Colorado Springs offers exceptional quality of life—immediate access to world-class outdoor activities, year-round recreation, and more than 300 days of sunshine each year.

Responsibilities:

Drive the physical design technical strategy across programs, including floorplanning, power architecture, and implementation trade-offs to meet PPA (performance, power, area) targets.
Lead, mentor, and grow a high-performing Physical Design team; set clear expectations for technical rigor, execution, and delivery.
Oversee physical implementation for digital, mixed-signal, and third-party IP—from block to subsystem to top-level integration—including place and route, timing closure, and power closure.
Coordinate closely with RTL/design, DFT/test, packaging, and systems teams to ensure clean handoffs, rapid issue resolution, and aligned delivery through tapeout.
Own and continuously improve the Physical Design flow, including methodology, automation, CI/regression infrastructure, and best-practice enablement for predictability and quality.
Lead physical verification and signoff (DRC/LVS, STA, power/IR/EM, reliability as applicable) and drive tape release readiness with clear signoff criteria.
Serve as the primary physical design interface to external CMOS/BiCMOS foundries and partners, ensuring alignment on PDKs, signoff requirements, and tapeout execution.
Own project execution across the physical design lifecycle—planning, resourcing, schedules, milestones, and risk mitigation—to deliver predictable tapeouts and product readiness.

Qualifications:

Must-have Qualifications

B.S. or M.S. in Electrical Engineering or Computer Engineering (or equivalent experience).
7+ years of relevant experience in digital ASIC physical design, including successful tape releases.
5+ years of project/program management experience, including planning, dependency management, risk tracking, and cross-team execution to tapeout.

Preferred Qualifications

Demonstrated people leadership, including mentoring and coaching engineers, developing future technical leaders, and building an inclusive, high-accountability culture.
Expertise in physical implementation and layout methodology, including timing closure, signoff, and power/performance/area optimization.
Working knowledge of DFT methodologies (e.g., scan insertion/test considerations) and how they impact physical design, closure, and tape release.
Strong EE fundamentals with experience spanning ASIC design concepts, IP integration, and CMOS/BiCMOS processes.
Strong teamwork and problem-solving skills, with clear written and verbal communication across engineering and program stakeholders.
Leadership skills to drive change and influence cross-functional teams toward execution goals, quality, and predictable delivery.
Sound technical judgment under schedule pressure, with a track record of making effective PPA trade-offs while maintaining signoff quality.

ITAR statement: This position requires access to certain goods, software, technology, or technical data subject to U.S. export control laws and regulations. Under these laws and regulations, U.S. persons (which includes U.S. citizens, U.S. nationals, lawful permanent residents, refugees, and asylees) working for Keysight can access export-controlled items without authorization from the U.S. government. For any individual who is not a U.S. person, Keysight may need authorization from the U.S. Department of State, U.S. Department of Commerce, or other appropriate federal agency before the individual can access export-controlled items. Employment in this position for non-U.S. persons is contingent on Keysight’s ability to obtain any required government authorizations.

We are unable to support visa sponsorship for this position.

MIN $151,000.00 - MAX $253,000.00

Most offers will be between the minimum and the midpoint of the Salary Range listed above.

#LI-MO1

Note: For other locations, pay ranges will vary by region

US Employees may be eligible for the following benefits:

Medical, dental and vision
Health Savings Account
Health Care and Dependent Care Flexible Spending Accounts
Life, Accident, Disability insurance
Business Travel Accident and Business Travel Health
401(k) Plan
Flexible Time Off, Paid Holidays
Paid Family Leave
Discounts, Perks
Tuition Reimbursement
Adoption Assistance
ESPP (Employee Stock Purchase Plan)

Careers Privacy Statement***Keysight is an Equal Opportunity Employer.***

Apply Now

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