Top 1967 Asic Design Jobs

Senior ASIC/SoC Physical Design Engineer
Everforth —San Jose, CA
- $150,000 - $250,000 a year
- Full-time
- Master's degree
- Analysis skills
- Mentoring
- Health insurance
- Dental insurance
Quick Apply
12d
Analog Design Manager
elix sourcing solutions —Cork, PA
- $100,000 - $140,000 a year
- Senior level
- Leadership
Master Physical Design Engineering Lead (up to $800k pkg)
Everforth —Fort Collins, CO
- Up to $800,000 a year
- Full-time
- No experience needed
- US work authorization
- Scripting
- Health savings account
- Employee stock purchase plan
Senior ASIC Design Engineer
Everforth —South Boston, MA
- $150,000 - $250,000 a year
- Full-time
- 5 years
- Office
- Master's degree
- Relocation assistance
- Health insurance
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12d
Sr. ASIC RTL Design Engineer
Everforth —Irvine, CA
- $150,000 - $250,000 a year
- Full-time
- 5 years
- Master's degree
- US work authorization
- Health insurance
- Dental insurance
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12d
ASIC Design Engineer
Sivaltech —Milpitas, CA
- Mid-level
- Bachelor's degree
Jr. ASIC Design Engineer
Fermilab —Batavia, IL
- $70,800 - $93,200 a year
- Full-time
- Hybrid work
- Background check
- Engineering
- Pass drug screening
- Disability insurance
- Health insurance
ASIC Design Engineer
Career Finders —San Diego, CA
- Mid-level
- Analysis skills
- Electrical Engineering
Digital IC Design Engineer
Microelectronics Research Development Corporation —Colorado
- Mid-level
- C++
- Doctor of Philosophy
ASIC Design Verification Engineer
Positron AI —Remote
- $200,000 - $350,000 a year
- Full-time
- Remote
- Master's degree
- 8 years
- Analysis skills
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ASIC Design Engineer - Fabric/Interconnect
Apple —Austin, TX
- $150,400 - $277,600 a year
- Bachelor of Science
- Mid-level
- 3 years
- Employee stock purchase plan
- Health insurance
ASIC Digital Design, Principal Engineer
Synopsys —Austin, TX
- $166,000 - $249,000 a year
- Analysis skills
- Continuous improvement
- Mentoring
ASIC Design Verification Engineer
K2 Space —Remote
- $130,000 - $200,000 a year
- Remote
- Bachelor of Science
- 3 years
- Senior level
- Paid parental leave
- Health insurance
ASIC Digital Design, Staff Engineer
Synopsys —Austin, TX
- $114,000 - $170,000 a year
- Master's degree
- Analysis skills
- Continuous improvement
ASIC Design and Integration Engineer
Apple —Beaverton, OR
- $184,700 - $324,800 a year
- Bachelor of Science
- 8 years
- Analysis skills
- Employee stock purchase plan
- Health insurance
Jr. Board Design Engineer
Lewiz communications —San Jose, CA
- Mid-level
- Electrical Engineering
ASIC Design Verification Engineer
Avicena Tech —Sunnyvale, CA
- $0 a year
- Full-time
- Mid-level
- 3 years
- Master's degree
Quick Apply
ASIC Design Engineer
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- Computer science
- Computer Science
- Bachelor of Science
ASIC Design Engineer
Blue Origin —Central, TX
- Full-time
- Background check
- Bachelor of Science
- DOT physical examination
- Paid parental leave
- Paid holidays
ASIC Digital Design, Sr Staff Engineer
Synopsys —Boxborough, MA
- $138,000 - $208,000 a year
- Data analysis skills
- Master's degree
- Analysis skills

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Senior ASIC/SoC Physical Design Engineer

Everforth -
San Jose, CA

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Job Details

Full-time
$150,000 - $250,000 a year
12 days ago

Benefits

Health insurance
Dental insurance
401(k)
Paid time off
Vision insurance
Life insurance

Qualifications

Tooling
Semiconductor electronics
SoC
Design engineering

Full Job Description

Senior ASIC/SoC Physical Design Engineer

Job Title: Senior ASIC/SoC Physical Design Engineer
Job Location: San Jose, CA or Irvine, CA
Compensation: $150K - $250K base DOE plus equity
Requirements: ASIC/SoC Physical Design, RTL-to-GDSII, Place and Route (P&R), Static Timing Analysis (STA), Synopsys, FinFET, Power Analysis

Position Overview
We are seeking a highly skilled Senior ASIC/SoC Physical Design Engineer to join our dynamic team. The ideal candidate will play a critical role in advancing our design methodologies and ensuring successful implementation of complex ASIC and SoC designs. You will be responsible for the physical design process, from RTL to GDSII, ensuring optimal performance, power, and area (PPA).

Key Responsibilities

Lead the physical design efforts for ASIC and SoC projects, ensuring high-quality implementations from RTL to GDSII.
Conduct Place and Route (P&R) activities, optimizing for performance, power, and area (PPA).
Perform Static Timing Analysis (STA) to ensure timing closure and meet design specifications.
Utilize Synopsys tools for physical design tasks and maintain up-to-date knowledge of FinFET technology.
Conduct power analysis and implement strategies to minimize power consumption in designs.
Collaborate with cross-functional teams to develop and refine physical design flows and methodologies.
Mentor and guide junior engineers in physical design best practices and tools.

Qualifications

Master's or Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
10+ years of experience in ASIC/SoC physical design roles.
Strong expertise in RTL-to-GDSII flow and physical design methodologies.
Proficient in Place and Route (P&R) and Static Timing Analysis (STA).
Experience with Synopsys EDA tools such as Design Compiler (DC), Fusion Compiler, IC Compiler (ICC2), Primetime etc.
Familiarity with FinFET technology and its implications on physical design.
Solid understanding of power analysis techniques and VLSI physical design principles.

Benefits

Vacation/PTO
Equity
Medical
Dental
Vision
Life Insurance
401k
For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. CyberCoders will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.This job was first posted by CyberCoders on 07/19/2026 and applications will be accepted on an ongoing basis until the position is filled or closed.Everforth CyberCoders is proud to be an Equal Opportunity Employer

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter . Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at [email protected] to make arrangements.

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