Top 1864 Asic Design Jobs

Lead ASIC DFT Engineer
Cyient —San Jose, CA
- $80 - $85 an hour
- Full-time
- Analysis skills
- Mentoring
- In-person
Quick Apply
Senior ASIC Digital Design Engineer
General Dynamics Mission Systems, Inc —Annapolis Junction, MD
- $142,166 - $150,000 a year
- Full-time
- Hybrid work
- Computer Science
- 3 years
- Master's degree
Senior FPGA / ASIC Design Assurance Engineer
Cyient —Melbourne, FL
- $101,037.27 - $121,679.30 a year
- Full-time
- Background check
- Computer Science
- 8 years
- Health savings account
- Relocation assistance
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11d
Physical Design Engineer
iTechStack Inc. —Mountain View, CA
- $110,000 - $150,000 a year
- Full-time
- Mid-level
- Master's degree
- In-person
- Health insurance
- Dental insurance
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Static Timing Analysis Engineer
iTechStack Inc. —San Jose, CA
- $100,000 - $150,000 a year
- Full-time
- 3 years
- Master's degree
- Bachelor's degree
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ASIC Design Engineer
Sivaltech —Milpitas, CA
- Mid-level
- Bachelor's degree
ASIC Design Engineer
Career Finders —San Diego, CA
- Mid-level
- Analysis skills
- Electrical Engineering
ASIC Digital Design, Staff Engineer
Synopsys —Austin, TX
- $114,000 - $170,000 a year
- Master's degree
- Analysis skills
- Continuous improvement
Jr. ASIC Design Engineer
Fermilab —Batavia, IL
- $70,800 - $93,200 a year
- Full-time
- Hybrid work
- Background check
- Engineering
- Pass drug screening
- Disability insurance
- Health insurance
FPGA/ASIC Verification Engineer
Grammar LLC —Rochester, NY
- $90,500 - $197,500 a year
- 8 hour shift
- Java
- Bachelor's degree
- Linux
- Paid holidays
- Disability insurance
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Analog Design Manager
elix sourcing solutions —Cork, PA
- $100,000 - $140,000 a year
- Senior level
- Leadership
ASIC Digital Design Engineer
General Dynamics Mission Systems, Inc —Annapolis Junction, MD
- $114,489 - $120,750 a year
- Full-time
- Hybrid work
- Mid-level
- Master's degree
- Continuous improvement
Digital IC Design Engineer
Microelectronics Research Development Corporation —Colorado
- Mid-level
- C++
- Doctor of Philosophy
ASIC Digital Design, Principal Engineer
Synopsys —Austin, TX
- $166,000 - $249,000 a year
- Analysis skills
- Continuous improvement
- Mentoring
ASIC Design Verification Engineer
Positron AI —Remote
- $200,000 - $350,000 a year
- Full-time
- Remote
- Master's degree
- 8 years
- Analysis skills
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ASIC Design Verification Engineer
K2 Space —Remote
- $130,000 - $200,000 a year
- Remote
- Bachelor of Science
- 3 years
- Senior level
- Paid parental leave
- Health insurance
ASIC Design Verification Engineer
Avicena Tech —Sunnyvale, CA
- $0 a year
- Full-time
- Mid-level
- 3 years
- Master's degree
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ASIC Digital Design, Staff Engineer -18138
Synopsys —Boxborough, MA
- $114,000 - $170,000 a year
- 5 years
- Data analysis skills
- Master's degree
9d
ASIC Design Engineer - Fabric/Interconnect
Apple —Austin, TX
- $150,400 - $277,600 a year
- Bachelor of Science
- Mid-level
- 3 years
- Employee stock purchase plan
- Health insurance
ASIC Design Verification Engineer (Santa Clara, CA)
Qualcomm —Austin, TX
- $126,700 - $190,100 a year
- Engineering
- Mid-level
- 3 years

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Lead ASIC DFT Engineer

Cyient -
San Jose, CA

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Job Details

Full-time | Contract
$80 - $85 an hour

Qualifications

Analog circuit design
Engineering development testing
Electronics functional testing
Integrated circuits (ICs)
Ramps
Analysis skills
SoC
System architecture design
Simulation tools
Root cause analysis
Test analysis
Python
Debugging
Cross-functional communication

Full Job Description

Title - Lead ASIC DFT Engineer

Location – San Jose, CA.

Duration - Contract

Job Description

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
Act as a technical escalation point for advanced DFT and post-silicon debug issues.
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

Strong hands-on experience in ASIC DFT with end-to-end ownership.
Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
Experience with MBIST implementation and verification; SMS experience preferred.
Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
Proven post-silicon debug and silicon bring-up experience.
Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

MBIST post-silicon validation.
ATPG simulations and fault coverage debug.
DFT RTL, DFD, DFT verification, and IP-level DFT integration.
DFT SDC creation and DFT timing closure support.
Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
TCL/PERL scripting for DFT automation, reporting, and debug.
Experience working across multiple ASIC technology nodes and complex product development cycles.
Familiarity with yield learning, diagnosis, and manufacturing test optimization.

Pay: $80.00 - $85.00 per hour

Work Location: In person

Quick Apply

Refine Your Search

Asic Design jobs

Lead ASIC DFT Engineer

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