Top 22 Asic Verification Intern Jobs

Digital Logic + Design Verification Graduate Co-Op Program (US - Fall 2026)
Marvell —Santa Clara, CA
- $35 - $70 an hour
- Full-time
- Office
- Analysis skills
- Electrical Engineering
- Paid holidays
- Health insurance
ASIC Design Engineer - New College Grad 2026
NVIDIA —Santa Clara, CA
- $100,000 - $189,750 a year
- Full-time
- Computer science
- Computer Science
- Bachelor of Science
4d
RTL Intern
Etched —San Jose, CA
- Research
- Office
- Machine learning
US 2026 Hardware - Digital Intern
TETRAMEM INC —San Jose, CA
- $35 - $45 an hour
- Internship
- Communication skills
- Entry level
Quick Apply
PD Intern
Etched —San Jose, CA
- Research
- Office
- Electrical Engineering
DFT Intern
Etched —San Jose, CA
- Research
- Office
- Electrical Engineering
DV Intern
Etched —San Jose, CA
- Research
- Office
- Machine learning
Physical Design Intern
SK hynix memory solutions America Inc. —San Jose, CA
- $35 - $45 an hour
- Schematics
- Data analysis skills
- Analysis skills
Design Engineering Intern
SK hynix memory solutions America Inc. —San Jose, CA
- $35 - $45 an hour
- Urgently hiring
- Computer Science
- Bachelor of Science
- Electrical Engineering
6d
Senior FPGA Verification Engineer
Ursa Major —Berthoud, CO
- $120,000 - $150,000 a year
- Remote
- 5 years
- Senior level
- Python
- Paid parental leave
- Health savings account
ASIC Design Engineer
Hewlett Packard Enterprise —Sunnyvale, CA
- $120,000 - $243,000 a year
- Full-time
- Office
- Master's degree
- Analysis skills
Sr. ASIC Design Engineer
Hewlett Packard Enterprise —Roseville, CA
- $153,500 - $310,500 a year
- Full-time
- Office
- Master's degree
- Analysis skills
Senior FPGA or ASIC Engineer
The MITRE Corporation —Bedford, MA
- Full-time
- 3 years
- Bachelor's degree
- Doctor of Philosophy
Senior Logic Design Engineer
NVIDIA —Santa Clara, CA
- $136,000 - $264,500 a year
- Full-time
- Computer science
- Computer Science
- 5 years
Principal ASIC Design Engineer
Hewlett Packard Enterprise —Sunnyvale, CA
- $174,000 - $352,500 a year
- Full-time
- Office
- Master's degree
- Analysis skills
Sr Engineering Manager - CRM
Medtronic —Minneapolis, MN
- $171,200 - $256,800 a year
- Full-time
- 5 years
- Office
- Travel
- Health savings account
- Employee stock purchase plan
9d
Electrical Engineer, ASIC Program Lead-CA
Synchron Inc. —San Diego, CA
- $160,000 - $260,000 a year
- Full-time
- Master's degree
- Mentoring
- In-person
- Commuter assistance
- Disability insurance
Quick Apply
Staff FPGA Design Engineer
Ursa Major —Berthoud, CO
- $150,000 - $180,000 a year
- Full-time
- Bachelor of Science
- Windows
- Analysis skills
- Paid parental leave
- Health savings account
Quick Apply
12d
Senior Analog IC Design Engineer
Medtronic —Mounds View, MN
- $108,000 - $162,000 a year
- Full-time
- Bachelor of Science
- Doctor of Philosophy
- US work authorization
- Health savings account
- Employee stock purchase plan
1d
Senior R & D Engineer, Electrical Engineering
Synchron Inc. —San Diego, CA
- $140,000 - $200,000 a year
- Full-time
- 8 years
- Senior level
- Electrical Engineering
- Commuter assistance
- Disability insurance
Quick Apply

I want to receive the latest job alert for Asic Verification Intern

By signing in to your account, you agree to SimplyHired's Terms of Service and consent to our Cookie and Privacy Policy.

Explore jobs in more locations

Asic Verification Intern jobs near

Design Engineer jobs in Santa Clara, CA

Electrical Engineer jobs in San Diego, CA

Designer jobs in San Jose, CA

Design Engineer jobs in Sunnyvale, CA

Principal Software Engineer jobs in Sunnyvale, CA

Digital Marketing Intern jobs in San Jose, CA

Senior Design Engineer jobs in Santa Clara, CA

Senior Engineering Manager jobs in Minneapolis, MN

Engineering Intern jobs in San Jose, CA

Senior R&D Engineer jobs in San Diego, CA

Digital Designer jobs in Santa Clara, CA

Interior Design jobs in Appleton, WI

Design Engineer jobs in Troy, MI

Design Intern jobs in Minneapolis, MN

Design Engineer jobs in Austin, TX

Instructional Design jobs in Indianapolis, IN

Design Engineer jobs in Fayetteville, AR

Design Engineer jobs in Fishers, IN

Senior Design Engineer jobs in Palmdale, CA

Senior Design Engineer jobs in Louisville, CO

Digital Logic + Design Verification Graduate Co-Op Program (US - Fall 2026)

Marvell -
Santa Clara, CA

Apply Now

Job Details

Full-time
$35 - $70 an hour

Benefits

Paid holidays
Health insurance
Dental insurance
Vision insurance

Qualifications

System architecture design

Full Job Description

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell’s Digital Logic & Design Verification Graduate Co-Op Program offers hands-on experience developing next-generation semiconductor technologies. This role is designed for students interested in digital IC design, SoC architecture, and verification methodologies, working on high-performance chips used in the scale up and scale out of AI data centers and other enterprise level applications.

This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. You'll be working on chips that ship to some of the largest enterprise applications globally.

Co-ops will gain exposure across the design lifecycle—from RTL development to simulation, verification, and silicon validation—while collaborating with cross-functional engineering teams.

What You Can Expect

Digital Design:

Contribute to RTL design and implementation of digital logic blocks for ASICs/SoCs
Support micro-architecture development, design specification, and implementation
Assist with synthesis, timing analysis, and design reviews
Collaborate with verification and physical design teams to ensure design quality

Design Verification:

Develop and execute verification test plans for digital and SoC designs
Build simulation environments, testbenches, and verification components
Debug simulation failures and analyze coverage
Work closely with design engineers to ensure functional correctness and performance

Cross-Functional:

Use industry-standard tools such as Verilog/SystemVerilog, UVM, and scripting languages
Automate workflows and analyze data using Python or similar tools
Support end-to-end chip development from architecture through validation
Collaborate with global engineering teams on leading-edge semiconductor products

What We're Looking For

Required:

Currently enrolled in a Master’s or PhD program in Electrical Engineering, Computer Engineering, or a related field
Strong foundation in digital logic design and computer architecture
Familiarity with HDL languages such as Verilog or SystemVerilog
Strong problem-solving, analytical, and communication skills

Preferred:

Exposure to UVM or formal verification methodologies
Experience with RTL design, simulation, or FPGA-based projects
Knowledge of scripting languages (Python, Perl, TCL, or shell)
Familiarity with SoC design concepts or high-speed interfaces (e.g., PCIe, DDR)
Prior internship or academic project experience in digital design or verification

Marvell's Co-Ops are onsite roles in office five days a week. This program is a good match for those that can step away from their academics for a semester. Please discuss this role with your trusted mentors and advisors prior to applying/interviewing to ensure alignment.

Expected Base Pay Range (USD)

35 - 70, $ per hour.

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights for our interns: medical, dental, and vision coverage, perks and discounts, robust mental health resources to prioritize emotional well-being, and paid holidays. Additional compensation may be available for intern PhD candidates. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

#LI-SC1

Apply Now

Refine Your Search

Asic Verification Intern jobs

Digital Logic + Design Verification Graduate Co-Op Program (US - Fall 2026)

ASIC Design Engineer - New College Grad 2026

RTL Intern

US 2026 Hardware - Digital Intern

PD Intern

DFT Intern

DV Intern

Physical Design Intern

Design Engineering Intern

Senior FPGA Verification Engineer

ASIC Design Engineer

Sr. ASIC Design Engineer

Senior FPGA or ASIC Engineer

Senior Logic Design Engineer

Principal ASIC Design Engineer

Sr Engineering Manager - CRM

Electrical Engineer, ASIC Program Lead-CA

Staff FPGA Design Engineer

Senior Analog IC Design Engineer

Senior R & D Engineer, Electrical Engineering

I want to receive the latest job alert for Asic Verification Intern

Explore jobs in more locations

Job Seeker Tools

Employer Tools

Browse

Stay Connected