Top 569 Cpu Physical Design Engineer Jobs

Lead SoC Design Engineer - Edge AI, High-Performance ASIC
Everforth —Los Altos, CA
- $200,000 - $300,000 a year
- Full-time
- Computer Science
- Master's degree
- US work authorization
- Health insurance
- Dental insurance
10d
CPU Physical Design Engineer
Intel —Austin, TX
- $141,910 - $269,100 a year
- Full-time
- Analysis skills
- Scripting
- Senior level
- Health insurance
Senior Physical Design Engineer (CPU)
Intel —Hillsboro, OR
- $141,910 - $269,100 a year
- Full-time
- Master's degree
- Senior level
- Electrical Engineering
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Senior CPU Core Physical Design Engineer
Intel —Hillsboro, OR
- $141,910 - $269,100 a year
- Full-time
- Hybrid work
- Computer science
- Computer Science
- Analysis skills
- Health insurance
CPU Physical Design Engineer
Apple —Beaverton, OR
- $184,700 - $324,800 a year
- CAD
- Bachelor of Science
- Bachelor's degree
- Employee stock purchase plan
- Health insurance
Physical Design Engineer - DSP Team
Qualcomm —Austin, TX
- $164,000 - $246,000 a year
- Computer Science
- CAD
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CPU Physical Design Engineer
Qualcomm —Austin, TX
- $179,000 - $268,400 a year
- Computer Science
- Master's degree
- Doctor of Philosophy
1d
Senior Physical Design and Timing Engineer
NVIDIA —Austin, TX
- $136,000 - $264,500 a year
- Full-time
- Hybrid work
- Bachelor of Science
- 3 years
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Physical Design Methodology CAD Engineer
Apple —Austin, TX
- $150,400 - $277,600 a year
- Bachelor of Science
- Mid-level
- 3 years
- Employee stock purchase plan
- Health insurance
CPU Core High Performance Physical Design Engineer
Advanced Micro Devices, Inc —Austin, TX
- Hybrid work
- CAD
- Senior level
- Electrical Engineering
Senior Physical Design Methodology Engineer, Innovus Flows
NVIDIA —Austin, TX
- $168,000 - $310,500 a year
- Full-time
- 7 years
- Analysis skills
- Senior level
CPU Physical Design Methodology and Optimization Engineer
Apple —Santa Clara, CA
- $184,700 - $324,800 a year
- Bachelor of Science
- Bachelor's degree
- Senior level
- Employee stock purchase plan
- Health insurance
CPU Physical Design Timing Engineer (Austin, TX)
Qualcomm —Austin, TX
- $122,500 - $183,700 a year
- Computer science
- Computer Science
- Mid-level
CPU Server Physical Design Clock Engineer
Qualcomm —Santa Clara, CA
- $142,200 - $213,400 a year
- Computer Science
- Mid-level
- Analysis skills
11d
CPU Design Methodology Engineer
NVIDIA —Austin, TX
- $136,000 - $264,500 a year
- Full-time
- 5 years
- Assembly
- Senior level
3d
CPU Circuit Design Engineer
Intel —Austin, TX
- $91,150 - $172,860 a year
- Full-time
- Master's degree
- 1 year
- Electrical Engineering
- Health insurance
CPU Core Physical Design Methodology Staff Engineer
Advanced Micro Devices, Inc —Austin, TX
- Hybrid work
- Data analysis skills
- System design
- Doctor of Philosophy
9d
CPU Memory Design Engineer
Intel —Austin, TX
- $164,470 - $269,100 a year
- Full-time
- Hybrid work
- Master's degree
- Analysis skills
- Doctor of Philosophy
- Health insurance
CPU Core Senior Physical Design Engineer
Intel —Folsom, CA
- $164,470 - $232,190 a year
- Full-time
- Hybrid work
- Computer science
- Computer Science
- Master's degree
- Health insurance
Principal Engineer, Power Design
Celestica —Austin, TX
- 11+ years
- Research
- Office

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Lead SoC Design Engineer - Edge AI, High-Performance ASIC

Everforth -
Los Altos, CA

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Job Details

Full-time
$200,000 - $300,000 a year
10 days ago

Benefits

Health insurance
Dental insurance
401(k)
Paid time off

Qualifications

CAD software
Electronics design
Verilog
SoC
Digital circuit design
Design engineering
System architecture design
Simulation tools
ARM

Full Job Description

Lead SoC Design Engineer - Edge AI, High-Performance ASIC

Job Title: Lead SoC Design Engineer - Edge AI, High-Performance ASIC
Job Location: Los Altos, CA - hybrid
Compensation: $200K - $300K base DOE plus equity
Requirements: SoC Microarchitecture, RTL Design, IP Integration (UCIe, DDR, CPU/GPU/NPU), ARM Cores, Memory Subsystems, AMBA Protocols (CHI, AXI, ACE, APB), HPC / Edge AI SoC

Position Overview
We're a well-funded, stealth startup building a next-generation, end-to-end computing platform powered by a custom, high-performance edge SoC on an advanced process node. By integrating flagship compute IP into an industry-leading design, we are building the optimized silicon foundation for our software platform from the ground up.

We're building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process. As our Lead SoC Design Engineer, you will develop the microarchitecture, own the critical tradeoffs required to hit aggressive PPA targets, and spearhead the implementation of key subsystems.

Key Responsibilities

Microarchitecture: Author detailed microarchitecture documents and drive reviews with software, architecture, and verification teams.
Drive PPA targets: Since we are developing a power-sensitive client product, you will drive performance/power tradeoffs using a data-driven approach to hit aggressive targets.
Partner with the verification team: Participate in reviews of verification and emulation test plans to ensure successful first-pass silicon.
RTL design: Own RTL coding, Lint/CDC/RDC checks, SDC and VCLP checks, and ensure that the design can be taken through physical design to meet frequency and power requirements.

Qualifications

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field; advanced degree preferred.
10+ years of experience in developing complex ASICs in advanced nodes.
Deep knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AXI-S/APB)
Experienced with Verilog, SystemVerilog, SystemVerilog Assertions (SVA).
Proficiency in writing and debugging SDC timing constraints, including multi-cycle paths, false paths, and clock domain crossing constraints.
Experience with industry-standard ASIC CAD tools for simulation, synthesis, STA, Lint, LEC, CDC, RDC, and power estimation.
Experience designing with multiple power domains and UPF.
Preferred Qualifications
Experience with commercial IP integration, ranging from high-speed interfaces (UCIe, DDR) to processing subsystems (CPU, GPU).
Experience working directly with ARM cores and subsystems.

Benefits

Medical/Dental/Vision benefits
Vacation/PTO
401K
Equity
Flexible Work Arrangements
For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. CyberCoders will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.This job was first posted by CyberCoders on 07/19/2026 and applications will be accepted on an ongoing basis until the position is filled or closed.Everforth CyberCoders is proud to be an Equal Opportunity Employer

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter . Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at [email protected] to make arrangements.

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