Top 12 Design Checker Jobs in Bothell, WA

ASIC Design Verification Engineer
K2 Space —Seattle, WA
- $130,000 - $200,000 a year
- Bachelor of Science
- 3 years
- Senior level
- Paid parental leave
- Health insurance
8d
ID Checker/Security Guard - Cannabis Retailer
Seattle Tonics —Seattle, WA
- From $21.30 an hour
- Part-time
- Background check
- Military
- Basic math
- Free parking
- Flexible schedule
Quick Apply
13d
Senior ASIC Design Verification Engineer
K2 Space —Seattle, WA
- $170,000 - $250,000 a year
- 5 years
- Bachelor of Science
- Analysis skills
- Paid parental leave
- Health insurance
8d
Drafter CAD Sr - New Glenn
Blue Origin —Seattle, WA
- $47.01 - $65.81 an hour
- Full-time
- Background check
- 7 years
- DOT physical examination
- Paid parental leave
- Paid holidays
7d
Principal ASIC Design Verification Engineer
K2 Space —Seattle, WA
- $190,000 - $285,000 a year
- Bachelor of Science
- Analysis skills
- Senior level
- Paid parental leave
- Health insurance
8d
IP Verification Engineer
TechBiz Global GmbH —Kirkland, WA
- Full-time
- Remote
- 5 years
- Senior level
- Electrical Engineering
Quick Apply
3d
Principal Memory Controller RTL Design Engineer
Microsoft —Redmond, WA
- $142,800 - $304,200 a year
- Full-time
- Background check
- Doctoral degree
- Computer Science
Staff Machine Learning Engineer, AI Agent Platform
GEICO —Seattle, WA
- $115,000 - $260,000 a year
- Full-time
- Computer Science
- Java
- AWS
Senior Software Engineer II
Compass —Seattle, WA
- $176,000 - $196,100 a year
- Computer science
- 7 years
- Computer Science
- Paid holidays
- Disability insurance
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Senior Software Engineer II
Modus Closing —Seattle, WA
- $176,000 - $196,100 a year
- Computer science
- 7 years
- Computer Science
- Paid holidays
- Disability insurance

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ASIC Design Verification Engineer

K2 Space
Seattle, WA

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Job Details

$130,000 - $200,000 a year
8 days ago

Benefits

Paid parental leave
Health insurance
Dental insurance
Paid time off
Parental leave
Vision insurance
Life insurance

Qualifications

Verification (System development task)
Electronics test plan development
Git
SoC
Microcontroller programming
Simulation tools
SystemVerilog
Debugging
Test Planning (Quality assurance practices)

Full Job Description

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we'd love for you to apply.

The Role

We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.

Responsibilities

Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
Participate in design reviews and microarchitecture discussions.

Qualifications

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
3+ years of experience in ASIC/SoC verification.
Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.
Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system (ex: Git).

Nice to Have

Experience with UVM-based testbench development, functional coverage, SystemVerilog assertions, and regression management.
Familiarity with developing and integrating reference models.
Understanding of RTL design flows and some industry standard interfaces (ex: APB/AHB/AXI).
Experience working in cross-functional, geographically distributed teams.
Experience in space, telecom, or RF/digital mixed systems is a plus.

Compensation and Benefits:

Base salary range for this role is $130,000 – $200,000 + equity in the company
Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!

If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.

Export Compliance

As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."

The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.

Equal Opportunity

K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

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Refine Your Search

Design Checker jobs in Bothell, WA

ASIC Design Verification Engineer

ID Checker/Security Guard - Cannabis Retailer

Senior ASIC Design Verification Engineer

Drafter CAD Sr - New Glenn

Principal ASIC Design Verification Engineer

IP Verification Engineer

Principal Memory Controller RTL Design Engineer

Staff Machine Learning Engineer, AI Agent Platform

Senior Software Engineer II

Senior Software Engineer II

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