Top 15343 Design Verification Engineer Jobs

FPGA/ASIC Verification Engineer
Grammar LLC —Rochester, NY
- $90,500 - $197,500 a year
- 8 hour shift
- Java
- Bachelor's degree
- Linux
- Paid holidays
- Disability insurance
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Senior Verification Engineer
Vibotek LLC —Austin, TX
- Full-time
- 7 years
- Senior level
- Communication skills
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DIGITAL DESIGN ENGINEER
Glint Tech Solutions LLC —Manassas, VA
- 5 years
- Master's degree
- Senior level
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RTL Design Engineer
iTechStack Inc. —Sunnyvale, CA
- $150,000 - $170,000 a year
- Full-time
- Quality control
- In-person
- Senior level
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Senior Wire Harness Design Engineer (EWIS)
Saronic Technologies —Austin, TX
- Full-time
- Office
- Mentoring
- Senior level
- Paid parental leave
- Paid holidays
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IP Verification Engineer
TechBiz Global GmbH —Kirkland, WA
- Full-time
- Remote
- 5 years
- Senior level
- Electrical Engineering
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13d
Logic Design and Verification Engineer
FLC Technology Group —Santa Clara, CA
- Bachelor of Science
- System design
- Mid-level
Harnessing Design Engineer
Impulse Space —Redondo Beach, CA
- $110,000 - $155,000 a year
- Full-time
- Mid-level
- 3 years
- SQL
- Health insurance
- Dental insurance
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Design Verification Engineer (remote position)
Correct Designs —Austin, TX
- Contract
- Mid-level
- 3 years
- Analysis skills
- Retirement plan
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Design Verification Engineer
Verilab —Lakeway, TX
- Full-time
- Computer science
- 7 years
- Computer Science
- AD&D insurance
- Paid holidays
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ASIC Design Verification Engineer
Avicena Tech —Sunnyvale, CA
- $0 a year
- Full-time
- Mid-level
- 3 years
- Master's degree
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Design Verification Engineer
Insilico —Irvine, CA
- Contract
- Senior level
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Senior Verification Engineer
TechBiz Global GmbH —Miami, FL
- Full-time
- Remote
- English
- Master's degree
- 8 years
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FPGA Design Verification Engineer
UST —Mountain View, CA
- $101,000 - $152,000 a year
- Mid-level
- Master's degree
- Fair chance
- Paid jury duty
- Health savings account
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Design Verification Engineer - SoC
Etched —San Jose, CA
- $150,000 - $275,000 a year
- Full-time
- Mid-level
- Office
- Analysis skills
- Health insurance
- Dental insurance
Design Engineer, Verification
GLOBALFOUNDRIES —Richardson, TX
- $86,000 - $184,000 a year
- Full-time
- English
- Mid-level
- Master's degree
Design Verification Engineer
Broadcom —Broomfield, CO
- $108,000 - $172,800 a year
- Full-time
- 6 years
- Schematics
- Bachelor of Science
- Employee stock purchase plan
- Paid holidays
Design Verification Engineer
Sivaltech —San Diego, CA
- Mid-level
- Electrical Engineering
ASIC Design Engineer
Career Finders —San Diego, CA
- Mid-level
- Analysis skills
- Electrical Engineering
Jr. ASIC Design Engineer
Fermilab —Batavia, IL
- $70,800 - $93,200 a year
- Full-time
- Hybrid work
- Background check
- Engineering
- Pass drug screening
- Disability insurance
- Health insurance

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FPGA/ASIC Verification Engineer

Grammar LLC -
Rochester, NY

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Job Details

Full-time
$90,500 - $197,500 a year

Benefits

Paid holidays
Disability insurance
Health insurance
Flexible spending account
Paid time off
Parental leave
Employee assistance program
401(k) matching
Flexible schedule

Qualifications

Embedded systems
FPGA
FPGA circuit design

Full Job Description

Role: FPGA/ASIC Verification Engineer

Job Schedule: 9/80: Employees work 9 out of every 14 days – totaling 80 hours worked – and have every other Friday off OR 5/8: Employees work 8 hours per day, 5 days a week

Job Description:

Join our team at the company and play a critical role in developing secure, cutting-edge tactical communication systems that protect those who protect us. As an FPGA Verification Engineer, you’ll collaborate with a talented, mission-driven team, verifying next-generation FPGA solutions for our radios used by military and first responders worldwide. This is a hands-on opportunity to grow your expertise in UVM, advanced verification methodologies, and complex communication systems—while enjoying work-life balance with flexible schedules and every other Friday off.

You will function primarily in an FPGA verification role, working in a cooperative team environment to verify and test embedded FPGA firmware for radio communication systems. We're seeking familiarity with a coverage-driven verification methodology from planning through closure as well as knowledge of industry standard interfaces. You will be required to analyze requirements, create test specifications/plans, write tests in System Verilog within a UVM test bench framework, and verify designs meet requirements. You will work with cross functional teams to verify FPGA designs for radio product development projects.

Essential Functions:

Perform FPGA design verification and validation of embedded electronic communication.

Assist in development of high-level and detailed verification test plans consistent with system requirements and specifications.

Develop self-checking test benches for FPGA design verification and validation using System Verilog.

Develop Agents, Test sequences, Cover groups, Predictors, Scoreboards.

Develop randomized and directed tests to achieve closure on functional coverage and provide feedback to team to reach functional coverage goals.

Develop high-level and detailed verification test plans and test benches consistent with system requirements and specifications.

Work with cross functional teams as needed to define and verify product and design requirements.

Prepare design and implementation reviews. Present technical briefings and status to internal and external customers.

Ability to obtain and maintain US Security Clearance.

Qualifications:

Bachelor’s Degree and minimum 6 years of prior relevant experience. Graduate Degree and a minimum of 4 years of prior related experience. In lieu of a degree, minimum of 10 years of prior related experience.

Experience developing and verifying FPGA/ASIC based embedded system solutions.

Preferred Additional Skills:

Demonstrated ability to analyze and debug FPGA firmware and related hardware issues.

Working knowledge of Ethernet Standard and design experience related to Ethernet packet processing.

Experience with cryptographic algorithms and cryptographic solutions for embedded communication systems.

Experience with Mentor Graphics Verification tools.

FPGA/ASIC RTL Design experience.

Proficiency in Object Oriented Programming (C++, JAVA).

Proven proficiency in FPGA/ASIC verification using System Verilog.

Working knowledge of UVM/OVM methodology.

Experience with Advanced Functional Verification tools to report functional coverage.

Experience with scripting languages (Bash, Perl, Python, Tcl).

Familiarity in working within Linux OS.

Familiarity with industry standard interfaces (Ethernet, AXI, SPI).

Solid technical writing skills and ability to communicate complex technical concepts/solutions both inside and outside of the organization.

Highly motivated, self-starter, who works well in team environments.

In compliance with pay transparency requirements, the salary range for this role in New York State is $90,500-$168,500. The salary range for this role in Maryland is $106,500 - $197,500. This is not a guarantee of compensation or salary, as final offer amount may vary based on factors including but not limited to experience and geographic location. Our company also offers a variety of benefits, including health and disability insurance, 401(k) match, flexible spending accounts, EAP, education assistance, parental leave, paid time off, and company-paid holidays. The specific programs and options available to an employee may vary depending on date of hire, schedule type, and the applicability of collective bargaining agreements.

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