Top 123 Dft Jobs | SimplyHired

Lead ASIC DFT Engineer
Cyient —San Jose, CA
- $80 - $85 an hour
- Full-time
- Analysis skills
- Mentoring
- In-person
Quick Apply
Lead ASIC DFT Engineer
Cyient —Remote
- From $100 an hour
- Full-time
- Remote
- Analysis skills
- Mentoring
- Senior level
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DFT Engineer - New College Grad
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- CAD
- Analysis skills
- Mentoring
Lead ASIC DFT Engineer
ZK Technologies —Remote
- $115,496.06 - $139,092.03 a year
- Contract
- Remote
- Analysis skills
- Mentoring
- Senior level
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New College Grad - Design Engineer, HBM DFT
Micron —Richardson, TX
- Master's degree
- In-person
- Electrical Engineering
- Employee stock purchase plan
- Paid holidays
DFT Engineer
Delos Data Inc —Palo Alto, CA
- $160,000 - $230,000 a year
- Full-time
- Remote
- 5 years
- Master's degree
- Analysis skills
- 401(k)
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Lead ASIC DFT Engineer
Acumenz Consulting Inc. —Remote
- $100,000.00 - $110,188.09 a year
- Full-time
- Remote
- Analysis skills
- Mentoring
- Senior level
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Senior DFT Engineer - LPU
NVIDIA —California
- $136,000 - $264,500 a year
- Full-time
- 5 years
- Senior level
- Electrical Engineering
Senior DFT Engineer
NVIDIA —Santa Clara, CA
- $168,000 - $310,500 a year
- Full-time
- Hybrid work
- 5 years
- Master's degree
- Analysis skills
DFT Engineers
Ambit Semiconductors —Texas
- 5 years
- Master's degree
- Bachelor's degree
Senior ASIC Timing Engineer, DFT
NVIDIA —Santa Clara, CA
- $136,000 - $264,500 a year
- Full-time
- Hybrid work
- Bachelor of Science
- Analysis skills
- Continuous improvement
Senior DFT Power Methodology Engineer
NVIDIA —Santa Clara, CA
- $196,000 - $310,500 a year
- Full-time
- 6 years
- Master's degree
- Analysis skills
Design for Test (DFT) Engineer
Info Way Group —San Francisco Bay Area, CA
- $50 - $60 an hour
- Full-time
- 5 years
- Master's degree
- In-person
Quick Apply
1d
ASIC DFT Engineer
Cisco Systems —San Jose, CA
- $135,800 - $252,000 a year
- Full-time
- Hybrid work
- 5 years
- Master's degree
- US work authorization
- Paid parental leave
- Paid holidays
12d
DFT Engineer
Qualcomm —Santa Clara, CA
- $140,000 - $210,000 a year
- Engineering
- Doctor of Philosophy
- In-person
10d
DFT Engineer
GLOBALFOUNDRIES —Richardson, TX
- $106,000 - $184,000 a year
- Full-time
- Mid-level
- Master's degree
- Analysis skills
DFT Engineer
Wipro Limited —Mountain View, CA
- $45,000 - $121,000 a year
- Pass drug screening
- Mid-level
- 3 years
- Disability insurance
- Health insurance
DFT Design Engineer
Cadence Design Systems —Austin, TX
- Full-time
- Mid-level
- Analysis skills
- 2 years
DFT Technical Leader
Cisco Systems —San Jose, CA
- $163,600 - $303,100 a year
- Full-time
- Hybrid work
- CAD
- Master's degree
- US work authorization
- Paid parental leave
- Paid holidays
10d
ASIC DFT CAD Technical Leader
Cisco Systems —San Jose, CA
- $163,600 - $303,100 a year
- Full-time
- CAD
- 8 years
- Team management
- Paid parental leave
- Paid holidays

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Lead ASIC DFT Engineer

Cyient -
San Jose, CA

Quick Apply

Job Details

Full-time | Contract
$80 - $85 an hour

Qualifications

Analog circuit design
Engineering development testing
Electronics functional testing
Integrated circuits (ICs)
Ramps
Analysis skills
SoC
System architecture design
Simulation tools
Root cause analysis
Test analysis
Python
Debugging
Cross-functional communication

Full Job Description

Title - Lead ASIC DFT Engineer

Location – San Jose, CA.

Duration - Contract

Job Description

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
Act as a technical escalation point for advanced DFT and post-silicon debug issues.
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

Strong hands-on experience in ASIC DFT with end-to-end ownership.
Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
Experience with MBIST implementation and verification; SMS experience preferred.
Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
Proven post-silicon debug and silicon bring-up experience.
Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

MBIST post-silicon validation.
ATPG simulations and fault coverage debug.
DFT RTL, DFD, DFT verification, and IP-level DFT integration.
DFT SDC creation and DFT timing closure support.
Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
TCL/PERL scripting for DFT automation, reporting, and debug.
Experience working across multiple ASIC technology nodes and complex product development cycles.
Familiarity with yield learning, diagnosis, and manufacturing test optimization.

Pay: $80.00 - $85.00 per hour

Work Location: In person

Quick Apply

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