Top 1948 Engineer Asic Design Jobs

Jr. ASIC Design Engineer
Fermilab —Batavia, IL
- $70,800 - $93,200 a year
- Full-time
- Hybrid work
- Background check
- Engineering
- Pass drug screening
- Disability insurance
- Health insurance
ASIC Design Engineer
Broadcom —Irvine, CA
- $108,000 - $172,800 a year
- Full-time
- 6 years
- Master's degree
- Fair chance
- Employee stock purchase plan
- Paid holidays
Design Verification Engineer (remote position)
Correct Designs —Austin, TX
- Contract
- Mid-level
- 3 years
- Analysis skills
- Retirement plan
Quick Apply
ASIC Design Verification Engineer
Broadcom —Irvine, CA
- $129,400 - $207,000 a year
- Full-time
- 3 years
- Master's degree
- Bachelor's degree
- Employee stock purchase plan
- Paid holidays
ASIC/FPGA Design Verification Engineer
Teradyne —North Reading, MA
- $123,100 - $196,900 a year
- 5 years
- Office
- Senior level
- Paid holidays
- Disability insurance
Design Engineer
Broadcom —Fort Collins, CO
- $60,200 - $96,300 a year
- Full-time
- Mid-level
- Analysis skills
- Fair chance
- Employee stock purchase plan
- Paid holidays
ASIC Design Verification Engineer
Positron AI —Remote
- $200,000 - $350,000 a year
- Full-time
- Remote
- Master's degree
- 8 years
- Analysis skills
Quick Apply
ASIC Design Verification Engineer
Avicena Tech —Sunnyvale, CA
- $0 a year
- Full-time
- Mid-level
- 3 years
- Master's degree
Quick Apply
Staff ASIC Digital Verification Design Engineer
Synopsys —Austin, TX
- $114,000 - $170,000 a year
- Master's degree
- Analysis skills
- Continuous improvement
Senior ASIC Physical Design Engineer
Johns Hopkins Applied Physics Laboratory (APL) —Laurel, MD
- $105,000 - $290,000 a year
- Full-time
- 6 years
- Continuous improvement
- Scripting
- Disability insurance
- Health insurance
ASIC Design Engineer
Sivaltech —Milpitas, CA
- Mid-level
- Bachelor's degree
ASIC Digital Design, Principal Engineer
Synopsys —Austin, TX
- $166,000 - $249,000 a year
- Analysis skills
- Continuous improvement
- Mentoring
Senior Design Verification Engineer (remote position)
Correct Designs —Austin, TX
- Contract
- 8 years
- Analysis skills
- In-person
- Retirement plan
Quick Apply
ASIC Digital Design, Staff Engineer
Synopsys —Austin, TX
- $114,000 - $170,000 a year
- Master's degree
- Analysis skills
- Continuous improvement
ASIC Implementation Engineer
Broadcom —San Jose, CA
- $120,000 - $192,000 a year
- Full-time
- 8 years
- Fair chance
- In-person
- Employee stock purchase plan
- Paid holidays
Design Verification Engineer
Broadcom —Broomfield, CO
- $108,000 - $172,800 a year
- Full-time
- 6 years
- Schematics
- Bachelor of Science
- Employee stock purchase plan
- Paid holidays
ASIC Design Engineer
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- Computer science
- Computer Science
- Bachelor of Science
ASIC Design Engineer
Career Finders —San Diego, CA
- Mid-level
- Analysis skills
- Electrical Engineering
Senior FPGA Design Engineer
HPR —Needham, MA
- $159,300 - $215,000 a year
- Full-time
- Computer science
- Computer Science
- 5 years
Quick Apply
Jr. Board Design Engineer
Lewiz communications —San Jose, CA
- Mid-level
- Electrical Engineering

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Jr. ASIC Design Engineer

Fermilab -
Batavia, IL

Apply Now

Job Details

Full-time
$70,800 - $93,200 a year

Benefits

Disability insurance
Health insurance
Dental insurance
Flexible spending account
Paid time off
Vision insurance
Life insurance
Retirement plan

Qualifications

Research and development in electrical engineering
CAD design (engineering design task)
Semiconductor electronics
Schematic development for electrical drafting
Radiation monitoring tools
Computer skills

Full Job Description

The expected hiring range for this position is:

$70,800.00-$93,200.00.

Please note that the pay range information is a general guideline only. The pay offered to a selected candidate will be determined based on factors such the scope and responsibilities of the position, qualifications of the selected candidate, business considerations, internal equity, and external market pay for comparable jobs.

About the Role:

We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic environments.

What your day-to-day as a Junior ASIC Design Engineer at Fermilab will look like:

Performing a leading role in Analog and RF ASIC design projects, while being able to contribute individually to major design tasks.
Developing design specifications for ASICs based on theoretical analyses and in conjunction with application needs.
Designing circuit networks using schematic entry and layout tools with full custom or timing-driven layout tools in Cadence CAD/EDA or a similar environment.
Models circuit networks and system components in hardware-description languages (Verilog-A and Verilog/SystemVerilog).
Building test benches and carries out analog and/or RF circuit simulations.
Executing physical and functional circuit and system verification.
Preparing documentation and participates in test-board designs and laboratory testing.
Delivering presentations internally, at national and international workshops, and at the topical conferences.
Performing other duties as assigned by supervisor.
Abiding by and being responsible for performing all duties in accordance with all environmental, health and safety regulations and practices pertinent to this position.

Skills and Attributes for Success:

Bachelor's degree in an applicable Engineering discipline from an ABET accredited institution.

Applicable Knowledge, Skills and Abilities Required:

Readiness for working on challenging projects that may have tight schedules.
Capability of working as part of a design team in a research and development environment
Experience with industry-standard front-end and back-end CAD/EDA design tools, such as Cadence, Synopsys and Mentor for the IC design.
Familiarity with principles of instrumentation for radiation detection with solid state or gaseous detectors and usages in extreme environments, like cryogenic or radiation harsh conditions
Strong computer skills and competence in performing analytical engineering calculations, in drawing schematics and in documentation.

Work Arrangement:
Please note that the described work arrangement is subject to change based on business needs and is not guaranteed to be final.

Hybrid: is a work arrangement in which an employee as part of an ongoing regular schedule, works at an alternative worksite in the United States (e.g., an employee’s residence) on some days and at the primary worksite on other days. Requires an approved hybrid work request for one or more days a week worked remotely within the United States on a routine basis.

Benefits/Perks:

Fermilab offers a competitive and comprehensive benefits program, including:

Medical, Dental, Vision and Flexible Spending Accounts

Paid time off
Life insurance
Short and Long-term disability insurance
Retirement benefits
Onsite day care

Why Fermilab:
Fermilab is America’s premier laboratory for particle physics and accelerator research, funded by the U.S. Department of Energy. We support discovery science experiments in Illinois and locations around the world, including deep underground mines in South Dakota and Canada, mountaintops in Arizona and Chile, CERN in Europe and the South Pole.

Pre-Employment Screening:

Drug-Free Workplace & Pre-Employment Screening

Fermilab is dedicated to fostering a safe, productive and drug-free environment. An offer of employment is contingent upon the successful completion of a background check and drug screening.

HSPD-12

In accordance with Homeland Security Presidential Directive 12 (HSPD-12) new employees are required to obtain and maintain a HSPD-12 Personal Identity Verification (PIV) Credential. To obtain this credential, new employees must successfully complete and pass a federal background check investigation. This investigation includes a declaration of illegal drug activities, including use, supply, possession, or manufacture. This includes marijuana and cannabis derivatives, which are still considered illegal under federal law, regardless of state laws. Failure to obtain or maintain such government access authorization could result in the withdrawal of a job offer or future termination of employment.

Foreign Government Sponsored Activities

Fermilab employees, and certain guest researchers and contractors, are subject to particular restrictions related to participation in Foreign Government Sponsored or Affiliated Activities, as defined and detailed in United States Department of Energy Order 486.1A. Such individuals will be asked to disclose any participation for review by Fermilab's Office of General Counsel.

REAL-ID Requirement for access to Fermilab Campus
Fermilab requires all members of the public to produce a REAL-ID, or equivalent, to access the Fermilab Campus for interviews or career events. A list of acceptable forms of ID can be found here: https://get-connected.fnal.gov/wp-content/uploads/2021/09/REALID-Documents.pdf. If a candidate is selected for an interview but does not possess any of the equivalent documents, we may schedule a virtual interview.

Equal Opportunity Statement

Fermilab is an equal opportunity employer. We evaluate qualified applicants without regard to race, color, religion, sex, age, national origin, disability, veteran status, genetic information, and other legally protected categories.

Apply Now

Refine Your Search

Engineer Asic Design jobs

Jr. ASIC Design Engineer

ASIC Design Engineer

Design Verification Engineer (remote position)

ASIC Design Verification Engineer

ASIC/FPGA Design Verification Engineer

Design Engineer

ASIC Design Verification Engineer

ASIC Design Verification Engineer

Staff ASIC Digital Verification Design Engineer

Senior ASIC Physical Design Engineer

ASIC Design Engineer

ASIC Digital Design, Principal Engineer

Senior Design Verification Engineer (remote position)

ASIC Digital Design, Staff Engineer

ASIC Implementation Engineer

Design Verification Engineer

ASIC Design Engineer

ASIC Design Engineer

Senior FPGA Design Engineer

Jr. Board Design Engineer

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