Top 761 Fpga/vhdl Design Engineer Jobs

Advanced ASIC FPGA Design Engineer for Crypto and Cross Domain Solutions
General Dynamics Mission Systems, Inc —Scottsdale, AZ
- $135,396 - $150,205 a year
- Full-time
- 3 years
- Master's degree
- Analysis skills
Digital Design Engineer - Level 5 - Linthicum
Northrop Grumman —Linthicum Heights, MD
- $185,900 - $278,900 a year
- Overtime
- Computer science
- 7 years
- Computer Science
- Paid holidays
- Disability insurance
RF Design Engineer
Johns Hopkins Applied Physics Laboratory (APL) —Laurel, MD
- $85,000 - $195,000 a year
- Full-time
- Bachelor of Science
- Mid-level
- Electrical Engineering
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- Health insurance
FPGA Engineer
Everforth —Chicago, IL
- Full-time
- Remote
- Mid-level
- Continuous improvement
- US work authorization
- Paid holidays
- Dental insurance
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FPGA Engineer
Everforth —Sunnyvale, CA
- Full-time
- Maintenance
- Mid-level
- Master's degree
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Junior FPGA Design Engineer
Carr Astronautics Corporation —Greenbelt, MD
- Computer science
- Computer Science
- Bachelor of Science
FPGA Design Engineer
University of Rochester —Rochester, NY
- $70,600 - $105,800 a year
- Full-time
- CAD
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- 3 years
FPGA Design Verification Engineer
UST —Mountain View, CA
- $101,000 - $152,000 a year
- Mid-level
- Master's degree
- Fair chance
- Paid jury duty
- Health savings account
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Senior FPGA Design Engineer
HPR —Needham, MA
- $159,300 - $215,000 a year
- Full-time
- Computer science
- Computer Science
- 5 years
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FPGA Engineer
Tiger IT Solutions —Greenwich, CT
- Mid-level
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Senior FPGA Engineer
Entegee —Manhattan Beach, CA
- $80 - $85 an hour
- Contract
- 3 years
- Analysis skills
- Bachelor's degree
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8d
FPGA Design Engineer II
HPR —Needham, MA
- $129,000 - $166,000 a year
- Full-time
- Computer science
- Computer Science
- Bachelor of Science
Quick Apply
Junior FPGA Engineer
KBR —Beavercreek, OH
- $90,000 - $110,000 a year
- Full-time
- Laboratory experience
- Linux
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FPGA Design Engineer
Tri-Star Design —Hopkinton, MA
- Senior level
- Electrical Engineering
- 10 years
Digital IC Design Engineer
Microelectronics Research Development Corporation —Colorado
- Mid-level
- C++
- Doctor of Philosophy
Principal FPGA Design Engineer
SiTime Corporation —Santa Clara, CA
- $164,800 - $226,600 a year
- Full-time
- Analysis skills
- Presentation skills
- Continuous improvement
- Health insurance
- Dental insurance
Quick Apply
Electrical Design Engineer
B&A Engineering —Costa Mesa, CA
- Full-time
- Mid-level
- 1 year
- Communication skills
Hardware Engineer, FPGA
Normal Computing Corporation —New York, NY
- $200,000 - $280,000 a year
- Full-time
- Hybrid work
- C++
- Senior level
- Python
13d
Hardware Design Engineer
Opal Kelly —Portland, OR
- 5 years
- Bachelor of Science
- System design
RTL Design Engineer (Silicon Engineering)
SpaceX —Irvine, CA
- $125,000 - $195,000 a year
- Extended hours
- Computer science
- Computer Science
- Mid-level
- Paid parental leave
- Employee stock purchase plan

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Advanced ASIC FPGA Design Engineer for Crypto and Cross Domain Solutions

General Dynamics Mission Systems, Inc -
Scottsdale, AZ

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Job Details

Full-time
$135,396 - $150,205 a year

Qualifications

Verification (System development task)
FPGA
Electrical technical documentation
Technical writing experience
FPGA circuit design

Full Job Description

Basic Qualifications :

Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience.

CLEARANCE REQUIREMENTS: Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Responsibilities for this Position:

What You'll Do

Architect and implement high-performance FPGA designs in VHDL and/or Verilog targeting Xilinx and Microchip device families.
Perform synthesis, place-and-route, and timing closure using Vivado or Libero, including advanced techniques such as pipelining, register retiming, floorplanning, and physical optimization
Develop and execute block-level simulations using QuestaSim/ModelSim with code coverage analysis (statement, branch, condition, expression)
Create self-checking testbenches for correctness verification
Design high-speed interfaces for inter-module communication and system integration
Collaborate with systems engineers, software developers, and verification engineers in an Agile development environment
Participate in design reviews, peer code reviews, and documentation of design specifications and interface control documents
Contribute to CI/CD pipeline development for automated synthesis, simulation regression, and coverage tracking
Support integration and lab bring-up activities, including on-target FPGA debug using ILAs and JTAG-based tools

Required Qualifications

Strong proficiency in VHDL and/or Verilog/SystemVerilog for synthesizable RTL design
Hands-on experience with Xilinx Vivado Design Suite or Microchip Libero for synthesis, implementation, and timing analysis
Experience targeting Xilinx and Microchip device families
Ability to achieve timing closure on designs at 300+ MHz clock rates
Experience with FPGA simulation tools (QuestaSim or ModelSim)
Proficiency in writing self-checking testbenches with automated pass/fail determination
Understanding of high-speed digital design principles: pipelining, clock domain crossing (CDC), metastability mitigation, and synchronous design
Experience with AXI-Stream, AXI4, or similar on-chip bus protocols
Ability to read and interpret timing reports, utilization summaries, and critical-path analysis output
Strong written and verbal communication skills for design documentation and technical presentations
S. Citizenship and ability to obtain/maintain a Secret security clearance

Preferred Qualifications

Experience with cryptographic algorithm implementation in hardware (AES, GCM, SHA, ECC, RSA, or similar)
Experience with high-speed serial interfaces: PCIe, Ethernet (10G/25G/100G), Fibre Channel, Aurora, or GTY/GTM transceivers
Experience with CI/CD pipelines for FPGA development (GitLab CI) including automated synthesis and regression testing
Proficiency in scripting languages (Tcl, Python, Bash) for build automation and design flow scripting
Experience with version control systems (GitLab) and collaborative development workflows
Experience with Xilinx IP cores: FIFO Generator, Clock Wizard, MIG/DDR controllers, DMA/Bridge subsystems
Experience with embedded processors in FPGA (MicroBlaze, Zynq PS, Versal AI Engine)

#CJ3

Salary Note: This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled. Combined Salary Range: USD $135,396.00 - USD $150,205.00 /Yr. Company Overview:

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans

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