Top 115 Functional Verification Co Op Jobs

Digital Logic + Design Verification Graduate Co-Op Program (US - Fall 2026)
Marvell —Santa Clara, CA
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Asst / Assoc / Professor, Department of Internal Medicine, Division of Gastroenterology & Hepatology
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- Medicine
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University of Cincinnati —Cincinnati, OH
- Full-time
- Mid-level
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Financial Administrator 2, Student Affairs
University of Cincinnati —Cincinnati, OH
- Online Application
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11d
Engineer Electronics - Communications
Northrop Grumman —San Diego, CA
- $91,800 - $137,600 a year
- Overtime
- Mid-level
- Master's degree
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Manufacturing Engineer - 3rd Shift / Weekend Crew - Plant 3
Howmet Aerospace —Whitehall, MI
- Full-time
- Bachelor of Science
- Engineering
- Laboratory experience
Quick Apply
Manufacturing Engineer - 2nd Shift - Plant 3
Howmet Aerospace —Whitehall, MI
- Full-time
- Bachelor of Science
- Engineering
- Mid-level
Quick Apply
Fall 2026 Co-Op - Design Verification Engineer
Cirrus Logic —Austin, TX
- Hybrid work
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Engineering Co-Op, R&D
Teleflex —Maple Grove, MN
- $23 - $25 an hour
- Microsoft Excel
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iRhythm Technologies, Inc. —San Francisco, CA
- $36 an hour
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Quick Apply
Launch Planning and Steering Co-op (Fall 2026)
BMW —Spartanburg, SC
- Full-time
- Computer Science
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Greenheck Group —Schofield, WI
- $19 - $24 an hour
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- Computer science
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Parker Hannifin Corporation —Akron, OH
- Customer service
- Electrical Engineering
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Cirrus Logic —Austin, TX
- Hybrid work
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Electrical Engineering Co-Op
Standex —Watertown, SD
- Microsoft Outlook
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- Electrical Engineering
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Mechanical Engineering Co-op - Fall 2026
Steris —Mentor, OH
- $23 - $27 an hour
- Full-time
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Co-Op Student - Puerto Rico Terminals
TOTE Resources LLC —San Juan, PR
- Background check
- Marketing
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3d

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Digital Logic + Design Verification Graduate Co-Op Program (US - Fall 2026)

Marvell -
Santa Clara, CA

Apply Now

Job Details

Full-time
$35 - $70 an hour

Benefits

Paid holidays
Health insurance
Dental insurance
Vision insurance

Qualifications

System architecture design

Full Job Description

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell’s Digital Logic & Design Verification Graduate Co-Op Program offers hands-on experience developing next-generation semiconductor technologies. This role is designed for students interested in digital IC design, SoC architecture, and verification methodologies, working on high-performance chips used in the scale up and scale out of AI data centers and other enterprise level applications.

This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. You'll be working on chips that ship to some of the largest enterprise applications globally.

Co-ops will gain exposure across the design lifecycle—from RTL development to simulation, verification, and silicon validation—while collaborating with cross-functional engineering teams.

What You Can Expect

Digital Design:

Contribute to RTL design and implementation of digital logic blocks for ASICs/SoCs
Support micro-architecture development, design specification, and implementation
Assist with synthesis, timing analysis, and design reviews
Collaborate with verification and physical design teams to ensure design quality

Design Verification:

Develop and execute verification test plans for digital and SoC designs
Build simulation environments, testbenches, and verification components
Debug simulation failures and analyze coverage
Work closely with design engineers to ensure functional correctness and performance

Cross-Functional:

Use industry-standard tools such as Verilog/SystemVerilog, UVM, and scripting languages
Automate workflows and analyze data using Python or similar tools
Support end-to-end chip development from architecture through validation
Collaborate with global engineering teams on leading-edge semiconductor products

What We're Looking For

Required:

Currently enrolled in a Master’s or PhD program in Electrical Engineering, Computer Engineering, or a related field
Strong foundation in digital logic design and computer architecture
Familiarity with HDL languages such as Verilog or SystemVerilog
Strong problem-solving, analytical, and communication skills

Preferred:

Exposure to UVM or formal verification methodologies
Experience with RTL design, simulation, or FPGA-based projects
Knowledge of scripting languages (Python, Perl, TCL, or shell)
Familiarity with SoC design concepts or high-speed interfaces (e.g., PCIe, DDR)
Prior internship or academic project experience in digital design or verification

Marvell's Co-Ops are onsite roles in office five days a week. This program is a good match for those that can step away from their academics for a semester. Please discuss this role with your trusted mentors and advisors prior to applying/interviewing to ensure alignment.

Expected Base Pay Range (USD)

35 - 70, $ per hour.

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights for our interns: medical, dental, and vision coverage, perks and discounts, robust mental health resources to prioritize emotional well-being, and paid holidays. Additional compensation may be available for intern PhD candidates. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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Refine Your Search

Functional Verification Co Op jobs

Digital Logic + Design Verification Graduate Co-Op Program (US - Fall 2026)

Co-Op: Electrical Engineering 1 1

Division Director, Assistant/Associate Professor, Clinical Geo, Hoxworth Transplantation Immunology

Hardware & Firmware Engineer

Asst / Assoc / Professor, Department of Internal Medicine, Division of Gastroenterology & Hepatology

Coordinator, Special Projects & Programs, Department of Radiology

Financial Administrator 2, Student Affairs

Engineer Electronics - Communications

Manufacturing Engineer - 3rd Shift / Weekend Crew - Plant 3

Manufacturing Engineer - 2nd Shift - Plant 3

Fall 2026 Co-Op - Design Verification Engineer

Engineering Co-Op, R&D

Electrical Test Engineering Co-op

Launch Planning and Steering Co-op (Fall 2026)

Customer Insights Co-op

Fall Engineering Co-Op

Fall 2026 Co-Op - Digital Design Engineer

Electrical Engineering Co-Op

Mechanical Engineering Co-op - Fall 2026

Co-Op Student - Puerto Rico Terminals

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