Top 974 Java Technical Lead Jobs in Mountain View, CA

Lead ASIC DFT Engineer
Cyient —San Jose, CA
- $80 - $85 an hour
- Full-time
- Analysis skills
- Mentoring
- In-person
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Lead Customer Engineer
Everforth —Santa Clara, CA
- $95,000 - $150,000 a year
- Full-time
- Computer science
- Computer Science
- Mid-level
- Dental insurance
- 401(k)
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Hardware Lead Design Engineer
TMP Worldwide India Private Limited for ERS US —Milpitas, CA
- $83,000 - $128,000 a year
- Email
- Analysis skills
- In-person
- Senior level
- AD&D insurance
- Paid holidays
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Lead Electrical Engineer
Coherent Corp. —Fremont, CA
- $100,625 - $172,250 a year
- Overtime
- Mid-level
- Office
- Doctor of Philosophy
AI GTM Transformation Lead
NetApp —San Jose, CA
- $196,350 - $292,600 a year
- 11+ years
- APIs
- Senior level
- Employee stock purchase plan
- Health insurance
4d
Lead Applications Engineer, Innovation Center (Customer Facing)
recruitAbility —San Jose, CA
- $150,000 - $175,000 a year
- Full-time
- Java
- Presentation skills
- Senior level
Lead Design Engineer - Semiconductor Lasers
The Hiring Method, LLC —Fremont, CA
- $100,625 - $172,250 a year
- 3 years
- Analysis skills
- Doctor of Philosophy
- Health insurance
- Dental insurance
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Lead Application Engineer (8146)
Advantest —San Jose, CA
- $129,000 - $200,000 a year
- Full-time
- Computer Science
- Software troubleshooting
- 5 years
- Health insurance
- Dental insurance
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Photonics Integration Engineer and Technical Lead (7401)
Advantest —San Jose, CA
- $150,000 - $231,850 a year
- Full-time
- Bachelor of Science
- Master's degree
- Analysis skills
- Health insurance
- Dental insurance
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Team Leader - Maintenance
Rich Products Corporation —Union City, CA
- $86,814 - $117,454 a year
- Bachelor of Science
- Engineering
- 3 years
- Health insurance
- Paid time off
Day Lead Technician - Full-Time
Sweeping Corporation of America —San Jose, CA
- $45 - $55 an hour
- Full-time
- Background check
- 18 years or older
- Clean driving record
- Paid holidays
- Disability insurance
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Lead Optical Product Engineer
Coherent Corp. —Fremont, CA
- $100,625 - $172,250 a year
- Full-time
- Bachelor of Science
- Office
- 3 years
Electrical Engineer Signal Integrity and Power Integrity Technical Lead (7400)
Advantest —San Jose, CA
- $129,650 - $200,400 a year
- Full-time
- Background check
- Bachelor of Science
- System design
- Health insurance
- Dental insurance
Quick Apply
Lead Histotechnologist
Lighthouse Lab Services —San Jose, CA
- $40 - $50 an hour
- Monday to Friday
- Mid-level
- High school diploma or GED
- Analysis skills
- Health insurance
- Dental insurance
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Facilities & Client Relations Manager / Lead Coordinator
LGTC Group —Burlingame, CA
- From $27 an hour
- Full-time
- Mid-level
- Administrative experience
- Bachelor's degree
- Dental insurance
- 401(k)
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Senior DevOps Lead Engineer (AI Acceleration)- Hybrid
Calance US —Santa Clara, CA
- $80 - $110 an hour
- Azure
- Computer Science
- Public speaking
Interior Design Team Leader (Luxury Residential)
Leoforce —San Jose, CA
- $125,000 - $160,000 a year
- Residential
- Senior level
- Communication skills
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Lead, IT Applications
Ross Stores —Dublin, CA
- $109,900 - $187,450 a year
- Hybrid work
- 7 years
- Office
- Analysis skills
7d
Senior Technical Product Manager - Data Governance Technology Platform Lead
U.S. Bank National Association —Cupertino, CA
- $148,495 - $174,700 a year
- Full-time
- Office
- 8 years
- Product management
- Paid holidays
- Disability insurance
Lead Manufacturing Technician
Nova Pneuma, Inc. —Fremont, CA
- $32 - $55 an hour
- 6 years
- Office
- High school diploma or GED
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Lead ASIC DFT Engineer

Cyient -
San Jose, CA

Quick Apply

Job Details

Full-time | Contract
$80 - $85 an hour

Qualifications

Analog circuit design
Engineering development testing
Electronics functional testing
Integrated circuits (ICs)
Ramps
Analysis skills
SoC
System architecture design
Simulation tools
Root cause analysis
Test analysis
Python
Debugging
Cross-functional communication

Full Job Description

Title - Lead ASIC DFT Engineer

Location – San Jose, CA.

Duration - Contract

Job Description

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
Act as a technical escalation point for advanced DFT and post-silicon debug issues.
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

Strong hands-on experience in ASIC DFT with end-to-end ownership.
Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
Experience with MBIST implementation and verification; SMS experience preferred.
Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
Proven post-silicon debug and silicon bring-up experience.
Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

MBIST post-silicon validation.
ATPG simulations and fault coverage debug.
DFT RTL, DFD, DFT verification, and IP-level DFT integration.
DFT SDC creation and DFT timing closure support.
Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
TCL/PERL scripting for DFT automation, reporting, and debug.
Experience working across multiple ASIC technology nodes and complex product development cycles.
Familiarity with yield learning, diagnosis, and manufacturing test optimization.

Pay: $80.00 - $85.00 per hour

Work Location: In person

Quick Apply

Refine Your Search

Java Technical Lead jobs in Mountain View, CA

Lead ASIC DFT Engineer

Lead Customer Engineer

Hardware Lead Design Engineer

Lead Electrical Engineer

AI GTM Transformation Lead

Lead Applications Engineer, Innovation Center (Customer Facing)

Lead Design Engineer - Semiconductor Lasers

Lead Application Engineer (8146)

Photonics Integration Engineer and Technical Lead (7401)

Team Leader - Maintenance

Day Lead Technician - Full-Time

Lead Optical Product Engineer

Electrical Engineer Signal Integrity and Power Integrity Technical Lead (7400)

Lead Histotechnologist

Facilities & Client Relations Manager / Lead Coordinator

Senior DevOps Lead Engineer (AI Acceleration)- Hybrid

Interior Design Team Leader (Luxury Residential)

Lead, IT Applications

Senior Technical Product Manager - Data Governance Technology Platform Lead

Lead Manufacturing Technician

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