Top 653 Memory Validation Engineer Jobs in California

Principal Design Verification Engineer - PCIe / High-Speed SoC
Everforth —Santa Clara, CA
- $200,000 - $250,000 a year
- Full-time
- Management
- Analysis skills
- C++
- Employee stock purchase plan
- Paid holidays
10d
Sr. ASIC RTL Design Engineer
Everforth —Irvine, CA
- $150,000 - $250,000 a year
- Full-time
- 5 years
- Master's degree
- US work authorization
- Health insurance
- Dental insurance
Quick Apply
10d
Manager Validation Engineer
West Valley Staffing Group —San Jose, CA
- $159,000 - $296,000 a year
- Hybrid work
- Team management
- Software development experience
- Senior level
- Health insurance
- Dental insurance
Quick Apply
Hardware Design Validation Engineer - Memory Subsystem
NVIDIA —Santa Clara, CA
- $108,000 - $212,750 a year
- Full-time
- Software troubleshooting
- Bachelor of Science
- Mid-level
Hardware Verification Engineer, Entry Level
Synopsys —Sunnyvale, CA
- $90,000 - $136,000 a year
- Contract
- Computer science
- Computer Science
- Master's degree
Lead Hardware Design Validation Engineer - Memory Subsystem
NVIDIA —Santa Clara, CA
- $168,000 - $322,000 a year
- Full-time
- Master's degree
- Scripting
- Linux
Engineering, Engineer
Synopsys —Sunnyvale, CA
- $90,000 - $136,000 a year
- Contract
- Computer science
- Computer Science
- Mid-level
ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning Acceleration
Annapurna Labs (U.S.) Inc. —Cupertino, CA
- $136,000 - $212,800 a year
- Full-time
- Computer science
- Computer Science
- Mid-level
- AD&D insurance
- Health insurance
DFT Engineer - New College Grad
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- CAD
- Analysis skills
- Mentoring
Senior High-Speed IO Validation Engineer
NVIDIA —Santa Clara, CA
- $136,000 - $258,750 a year
- Full-time
- Schematics
- Bachelor of Science
- 3 years
Principal DRAM Architect – GPU Memory Solutions
NVIDIA —Santa Clara, CA
- $272,000 - $431,250 a year
- Full-time
- Hybrid work
- System design
- 11+ years
- Doctor of Philosophy
Staff Engineer, Partner Lab Support
Micron —San Jose, CA
- $122,000 - $302,000 a year
- Full-time
- Mid-level
- Employee stock purchase plan
- Paid holidays
Lead Hardware Design Validation Engineer
NVIDIA —Santa Clara, CA
- $168,000 - $322,000 a year
- Full-time
- Bachelor of Science
- 8 years
- Travel
Memory Component Engineer Hybrid, San Jose, CA
Cisco Systems —San Jose, CA
- $128,200 - $210,500 a year
- Full-time
- Hybrid work
- 5 years
- Bachelor of Science
- Conflict management
- Paid parental leave
- Paid holidays
Senior Memory Subsystem Firmware Engineer
NVIDIA —Santa Clara, CA
- $152,000 - $241,500 a year
- Full-time
- Hybrid work
- Computer science
- Computer Science
- Bachelor of Science
Hardware Validation Engineer
Super Micro Computer —San Jose, CA
- $105,000 - $116,000 a year
- Laboratory experience
- Mid-level
- Assembly
Lab Engineering Technician
Intel —Santa Clara, CA
- $72,810 - $102,790 a year
- Full-time
- Computer science
- Computer Science
- Bachelor of Science
- Health insurance
3d
Staff Machine Learning Engineer
Pinterest —San Francisco, CA
- $189,308 - $389,753 a year
- Computer science
- 7 years
- Computer Science
DDRSS Validation Engineer (RTL + Silicon Debug)
Qualcomm —San Diego, CA
- $140,000 - $210,000 a year
- 6 years
- Engineering
- Doctor of Philosophy
Senior Post Silicon Low Power Integration Engineer
NVIDIA —Santa Clara, CA
- $168,000 - $310,500 a year
- Full-time
- Hybrid work
- Computer Science
- Bachelor of Science
- System design

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Principal Design Verification Engineer - PCIe / High-Speed SoC

Everforth -
Santa Clara, CA

Apply Now

Job Details

Full-time
$200,000 - $250,000 a year
10 days ago

Benefits

Employee stock purchase plan
Paid holidays
Health insurance
Dental insurance
401(k)
RSU
Paid time off
Vision insurance
Opportunities for advancement
Life insurance

Qualifications

Automation
SoC
SystemVerilog
Python

Full Job Description

Principal Design Verification Engineer - PCIe / High-Speed SoC

Job Title: Principal Design Verification Engineer - PCIe / High-Speed SoC
Location: Santa Clara, CA
Compensation: $200K - $250K base DOE plus bonus and RSUs ($300K - $350K+ total comp.)
Requirements: Design Verification, High-Speed SoC, PCIe / UALink / SerDes, SystemVerilog, UVM

Position Overview
We are seeking a Principal Design Verification Engineer with deep expertise in PCIe and high-speed SoC verification to lead verification efforts for next-generation multi-core SoCs. This role will own verification planning, architecture, and execution for complex IP (PCIe, SerDes, UALink, interconnect) and full-chip integrations, drive closure of functional coverage and sign-off criteria, and mentor a team of verification engineers. The ideal candidate combines strong hands-on technical skills (SystemVerilog/UVM, Python, C++, scripting) with proven leadership in large-scale SoC verification projects and experience with EDA verification tool flows.

Key Responsibilities

Define and drive verification strategy and plans for PCIe IP, SerDes subsystems, and high-speed SoC integrations to achieve tape-out quality sign-off.
Lead development of modular, reusable UVM/ SystemVerilog verification environments and testbenches for IP and subsystem-level verification; ensure portability and maintainability.
Create and maintain directed and constrained-random test suites, protocol-aware tests for PCIe root/endpoint behavior, error handling, and power/clock domain interactions.
Develop and maintain functional coverage models and closure plans; analyze coverage holes and direct debugging and rework to meet coverage targets.
Architect and implement bring-up and silicon validation support, including creation of bring-up tests, debug scripts, and root-cause analysis for silicon failures.
Drive cross-functional collaboration with architects, RTL designers, firmware/driver teams (ARM), and physical design to resolve verification issues and ensure correct integration.
Leverage and extend EDA verification tool flows (simulation, emulation/FPGA prototypes, static checks, formal) and manage regression infrastructure for large-scale verification runs.
Develop and maintain verification automation (Python, Perl, shell), including test orchestration, result parsing, and metrics dashboards.
Mentor and lead verification engineers, perform code/review sessions, set best practices for assertions, UVM factories, scoreboards, and reuse methodologies.
Evaluate and integrate third-party verification IP and tools (e.g., protocol analyzers, link-layer tools such as UALink) to accelerate verification and validation.
Contribute to performance and power verification scenarios, multi-core coherency testing, and system-level scenarios involving DMA, interrupts, and memory subsystems.

Qualifications

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field; PhD a plus.
10+ years of experience in design verification with a strong focus on SoC and high-speed interfaces (PCIe, UALink, Ethernet, SerDes etc.); proven track record leading verification for complex silicon projects.
Deep knowledge of PCIe protocol (link training, LTSSM, transaction/completion semantics) and hands-on experience verifying PCIe IP (root/endpoint/Switch).
Extensive experience with SystemVerilog and UVM for verification environment development and testbench architecture.
Strong scripting and automation skills (Python required; Perl and shell scripting desirable) and proficiency in C++ for verification components or tools.
Hands-on experience with EDA verification tools (simulation like Synopsys VCS/Questa/Incisive, emulation, formal tools, coverage analysis tools) and large regression/CI workflows.
Experience with SerDes, PHY-level behaviors (link equalization, PAM-n, BER testing), and high-speed link characterization.
Familiarity with ARM-based firmware/bring-up flows and validating multi-core SoC interactions (interconnects, coherency, cache behavior).
Proven expertise in functional coverage-driven verification, assertion-based verification (SVA/PSL), and coverage closure methodologies.
Experience with third-party tools and link analyzers such as UALink or similar protocol tools is a plus.
Strong problem-solving, debugging and root-cause analysis skills; able to drive issues to closure in fast-paced environments.
Excellent communication and leadership skills with experience mentoring engineers and coordinating cross-team verification activities.

Benefits

Comprehensive medical, dental, and vision plans
Life insurance and disability plan options
401(k)
RSUs
ESPP
Paid company-selected holidays & floating holidays
PTO - generous time off programs
Career growth opportunities
For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. CyberCoders will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.This job was first posted by CyberCoders on 07/18/2026 and applications will be accepted on an ongoing basis until the position is filled or closed.Everforth CyberCoders is proud to be an Equal Opportunity Employer

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter . Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at [email protected] to make arrangements.

Apply Now

Refine Your Search

Memory Validation Engineer jobs in California

Principal Design Verification Engineer - PCIe / High-Speed SoC

Sr. ASIC RTL Design Engineer

Manager Validation Engineer

Hardware Design Validation Engineer - Memory Subsystem

Hardware Verification Engineer, Entry Level

Lead Hardware Design Validation Engineer - Memory Subsystem

Engineering, Engineer

ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning Acceleration

DFT Engineer - New College Grad

Senior High-Speed IO Validation Engineer

Principal DRAM Architect – GPU Memory Solutions

Staff Engineer, Partner Lab Support

Lead Hardware Design Validation Engineer

Memory Component Engineer Hybrid, San Jose, CA

Senior Memory Subsystem Firmware Engineer

Hardware Validation Engineer

Lab Engineering Technician

Staff Machine Learning Engineer

DDRSS Validation Engineer (RTL + Silicon Debug)

Senior Post Silicon Low Power Integration Engineer

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