Top 38905 Physical Design Engineer Jobs

Staff Physical Design Engineer ($300-400k pkg)
Everforth —Fort Collins, CO
- $350,000 - $400,000 a year
- Full-time
- Office
- US work authorization
- Fair chance
- Health savings account
- Employee stock purchase plan
Quick Apply
Physical Design Engineer
Insilico —San Jose, CA
- Scripting
- Senior level
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Physical Design Engineer
Cisco Systems —San Jose, CA
- $109,900 - $200,100 a year
- Full-time
- Mid-level
- Master's degree
- Analysis skills
- Paid parental leave
- Paid holidays
Physical Design Engineer
NVIDIA —Westford, MA
- $116,000 - $218,500 a year
- Full-time
- CAD
- 3 years
- Master's degree
ASIC Physical Design Engineer, Netlisting - New College Grad 2026
NVIDIA —Austin, TX
- $116,000 - $218,500 a year
- Full-time
- Mid-level
- Doctor of Philosophy
- Experience equivalent to degree accepted
Engineer, ASIC Physical Design
Micron —Minneapolis, MN
- $142,506.01 - $176,000.00 a year
- Part-time
- System design
- Master's degree
- Scripting
- Employee stock purchase plan
- Paid holidays
SoC Physical Design Engineer, PnR
Apple —Beaverton, OR
- Bachelor of Science
- Analysis skills
- Bachelor's degree
Verification Engineer - Aeromechanical (Design & Test)
Pivotal —Palo Alto, CA
- $115,000 - $145,000 a year
- Full-time
- Writing skills
- Mid-level
- Master's degree
- Health insurance
- Dental insurance
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Staff. Physical Design Engineer
Qualcomm —San Diego, CA
- $140,000 - $210,000 a year
- Computer Science
- Engineering
- Mid-level
R&D Engineer Physical Design
Broadcom —San Jose, CA
- $143,800 - $230,000 a year
- Full-time
- Bachelor of Science
- Fair chance
- Senior level
- Employee stock purchase plan
- Paid holidays
Physical Design Engineer II (Silicon Engineering)
SpaceX —Palo Alto, CA
- $155,000 - $210,000 a year
- Extended hours
- Computer science
- Computer Science
- Mid-level
- Paid parental leave
- Employee stock purchase plan
RTL / Physical Design Engineer
Persimmons —San Jose, CA
- Full-time
- Mid-level
- 3 years
- Master's degree
- 401(k)
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CPU Physical Design Engineer
Intel —Austin, TX
- $105,650 - $200,340 a year
- Full-time
- Mid-level
- Analysis skills
- Scripting
- Health insurance
Senior Engineer, Physical Design (ASIC/SoC Place & Route) (Austin, TX)(5560)
TSMC —Austin, TX
- $106,500 - $162,000 a year
- Hybrid work
- 7 years
- Computer Science
- Office
Physical IC Design Engineer
Broadcom —San Jose, CA
- Full-time
- 6 years
- Master's degree
- Fair chance
- Employee stock purchase plan
- Paid holidays
6d
Staff Physical Design Engineer
Lightmatter —Boston, MA
- $186,000 - $218,000 a year
- Full-time
- 8 years
- Senior level
- Electrical Engineering
- Commuter assistance
- AD&D insurance
Silicon Physical Design Engineer
Google —Sunnyvale, CA
- $116,000 - $166,000 a year
- Full-time
- Computer science
- Computer Science
- Mid-level
11d
Design Engineer, Verification
GLOBALFOUNDRIES —Richardson, TX
- $86,000 - $184,000 a year
- Full-time
- English
- Mid-level
- Master's degree
Senior ASIC Physical Design Engineer
Cisco Systems —San Jose, CA
- $146,700 - $277,600 a year
- Full-time
- Master's degree
- Analysis skills
- Doctor of Philosophy
- Paid parental leave
- Paid holidays
CPU Core High Performance Physical Design Engineer
Advanced Micro Devices, Inc —Austin, TX
- Hybrid work
- CAD
- Senior level
- Electrical Engineering

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Staff Physical Design Engineer ($300-400k pkg)

Everforth -
Fort Collins, CO

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Job Details

Full-time
$350,000 - $400,000 a year

Benefits

Health savings account
Employee stock purchase plan
Disability insurance
Health insurance
Dental insurance
Flexible spending account
Paid time off
Vision insurance
401(k) matching

Qualifications

Cross-functional collaboration
Shell Scripting
Cross-functional communication

Full Job Description

Staff Physical Design Engineer ($300-400k pkg)

Staff ASIC Engineer (Physical Design OR STA)

Total package up to $400k (Base up to $200k + bonus + stock)

Total first year realistic income $350-400k

Locations: San Jose, CA, Irvine, CA or Fort Collins, CO

Introduction

Are you an experienced ASIC engineer with strong expertise in physical design or STA, and a passion for working on bleeding-edge AI and high-performance silicon? Do you enjoy diving into complex EDA reports, identifying issues early, and collaborating with top-tier engineering teams to deliver next-generation chips?

If you're excited about contributing to advanced AI/ML accelerators and infrastructure silicon, this role offers the opportunity to work at the forefront of semiconductor innovation.

Top Reasons to Work With Us

Support customers building next-generation AI/ML, HPC, and infrastructure ASICs
Work on cutting-edge silicon for AI workloads, including large-scale compute and accelerator architectures
Collaborate with highly experienced cross-functional engineering teams
Gain exposure to advanced nodes, chiplet architectures, and high-performance design methodologies
Contribute to customer program success from early engagement through production
Be part of a collaborative, technically strong environment

The Role / Responsibilities

As a Staff ASIC Engineer, you will work closely with senior engineers and internal teams to support customer ASIC programs focused on advanced AI and compute silicon. This is a primarily hands-on role, with opportunities to grow into broader technical ownership over time.

Your responsibilities will include:

Assisting in the execution of customer AI/ML ASIC programs across design, test, packaging, fabrication, bring-up, and production
Supporting customer teams with EDA tools, design flows, and methodology best practices for high-performance silicon
Helping identify risks in quality, schedule, or dependencies and contributing to mitigation efforts
Running physical design or STA validation flows to ensure designs meet stringent tape-out standards for advanced nodes
Collaborating with cross-functional teams to resolve complex implementation challenges in AI and compute architectures
Staying current with emerging AI silicon trends, IP, and implementation methodologies
Supporting program communication across engineering and internal partner teams

Essential Skills

Experience with multiple ASIC tape-outs (advanced nodes preferred)
Strong understanding of PPA tradeoffs, especially in high-performance designs
Knowledge of low power design and power management in compute-intensive systems
Hands-on experience in physical design or STA, including relevant EDA tools and flows
Exposure to broader ASIC flows (logic simulation, test, packaging)
Scripting experience (TCL, shell, or similar)
Strong communication and collaboration skills

Bonus Points For

Experience with AI/ML accelerators, HPC, or large-scale compute SoCs
Exposure to SERDES or high-speed interfaces
Experience in RTL design, microarchitecture, or front-end flows
Knowledge of DFT (scan, MBIST, repair)

Benefits

Health, dental, and vision insurance
Life and disability insurance
FSA and HSA
401k with match
ESPP
Generous PTO
Annual bonus from 15-30% (depending on your level)
VERY generous stocks!
For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. This job was first posted by CyberCoders on 07/21/2026 and applications will be accepted on an ongoing basis until the position is filled or closed.Everforth CyberCoders is proud to be an Equal Opportunity Employer

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter . Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at [email protected] to make arrangements.

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