Top 1426 Senior Embedded Developer Jobs

Senior Embedded Systems Engineer
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- $111,123 - $123,470 a year
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- Mid-level
- Master's degree
- Profit sharing
- Health savings account
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Senior Embedded Systems Engineer

Micro Control Company -
Fridley, MN

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Job Details

Full-time
$111,123 - $123,470 a year

Benefits

Profit sharing
Health savings account
Disability insurance
Health insurance
Dental insurance
401(k)
Tuition reimbursement
Paid time off
Vision insurance

Qualifications

Project engineering
Git
Version control systems
RTOS
Linux
Embedded C
Project Development
Python

Full Job Description

**This salary information serves as a general guideline. Final offers are based on various factors, including qualifications, skills, experience, and other job-related criteria.

Benefits:

Paid Time Off, Health Insurance, Health Savings Account (HSA), Dental Insurance, Vision Insurance, 401(K) with Roth option, Life & Disability Insurance, Tuition Reimbursement & Discretionary Profit-Sharing Bonus.

Job Summary:

This position will report to our Electronics Engineering Manager in the System Design Department and is responsible for the design, implementation, and optimization of our microprocessor-based platforms, custom hardware firmware and high-level software, ensuring deterministic performance, and stability. In addition, they will act as the lead integrator for firmware projects, mentoring junior developers and ensuring code quality across the department.

Key Responsibilities:

Hardware Design: design circuits, select components, enter schematics, and guide PCB routing.
RTOS Implementation: Configure and optimize real-time operating system environments to meet system-level timing and performance requirements.
Firmware Development: Author robust, modular firmware in C/C++ for microprocessors, high-speed buses, and peripheral interfaces.
System Integration: Lead onsite board-bring-up sessions, utilizing Oscilloscopes and Protocol Analyzers to solve hardware-to-firmware timing issues.
Diagnostic & Test: Design diagnostic templates and automated Python-based test suites for hardware verification and regression testing.
Process Leadership: Perform peer code reviews and enforce version control (Git) and documentation standards.

Required Qualifications:

Bachelor’s degree in Electrical Engineering,Computer Engineering or related field, and/or equivalent experience.
4 years relevant engineering experience.
Thorough knowledge of RTOS fundamentals, including multi-threaded environments, interrupt handling, and real-time scheduling.
Proficient in C/C++, Python, Git, Linux, Real-Time OS frameworks, Xilinx or Altera FPGA flow.
Exceptional verbal and written communication skills.
Excellent prioritization and project development skills with ability to manage multiple tasks and projects.
Ability to travel up to 5% domestically and internationally.

Preferred Qualifications:

Master’s degree
Experience implementing stacks/drivers for High-Speed Protocols (Ethernet, PCIe, or USB-C).
Experience configuring and tuning DDR3/4/5 memory controllers, including JEDEC initialization, PHY training (read/write leveling), and performance optimization.
Strong Verilog/HDL literacy with the ability to collaborate with FPGA engineers to define memory-map interfaces (AXI, SPI, I2C, custom, etc.)
Ability to navigate Cadence Allegro schematics to assist in debugging.

Physical Demands:

The physical demands described here are representative of those that must be met by an individual to successfully perform the essential functions of this position. Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions.

Must be able to perform sedentary work, including sitting for extended periods of time.
Ability to periodically stand, walk, crouch, stoop, bend, and reach across all planes.
Ability to operate a computer and other office productivity equipment.
Specific vision abilities required include close vision, distance, vision, and ability to adjust focus.
May be required to lift and/or move objects up to 50 pounds, 0 - 10% of time.

#SAL

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