Verilog jobs - Folsom, CA

Mavensoft Technologies - Folsom, CA

3+ yrs experience with RTL development with Verilog. Project Description: -Custom test ... -FPGA synthesis experience. -Experience with verilog design language Experience with...

eTech Recruiters, Inc. Dba eTech Resources. - Folsom, CA

Verification Other Skills: Validation; Verilog Minimum Requirements: - Experience (> ... and methodologies - Expertise in Verilog*, SystemVerilog*, Tcl/Perl scripting,...

Mavensoft Technologies - Folsom, CA

Title: Validation Engineer ( Perl, Tcl, Verilog) (Mid-Level) Location:Folsom, CA ... and methodologies. - Expertise in Verilog*, SystemVerilog*, Tcl/Perl scripting,...

Mavensoft Technologies - Folsom, CA

info, and salary requirements. Title: Verilog Verification Engineer ... and methodologies. - Expertise in Verilog*, SystemVerilog*, Tcl/Perl scripting,...

Experis - Folsom, CA

3+ yrs experience with RTL development with Verilog Project Description: Custom test ... FPGA synthesis experience Experience with Verilog design language Experience with...

CompuCom Systems - Folsom, CA

ng skills BS degree in Electrical Engineering, Computer Engineering, or Computer Science Additional Skills (Nice to Have): Perl Tcl/Tk Verilog C/C++ EDA tool experience in...

Mindlance - Folsom, CA

FPGA synthesis experience. Experience with verilog design language Experience with simulation environment and test bench development. Additional Skills Desired (Nice to Have):...

Kelly Engineering Resources - Folsom, CA

My client has a contract position for you! Verilog and Debug; TEST CASE DVLPMT.; ... PCIe domain expertise, VCS/Modelsim, System Verilog/Verilog, Problem solving skills,...

Chip Source - Sacramento, CA

icro-architecture. Develop and implement block level RTL, Synthesis, Timing, and Chip architecture. Participate in design of communications SoCs. Verilog design and verification...

Volt Information Sciences - Folsom, CA

FPGA synthesis experience Experience with Verilog design language Experience with simulation environment and test bench development Debug in a lab environment using logic...