Verilog jobs - Minneapolis, MN

Chip Source - Minneapolis, MN

icro-architecture. Develop and implement block level RTL, Synthesis, Timing, and Chip architecture. Participate in design of communications SoCs. Verilog design and verification...

Seagate - Shakopee, MN

Designing in Verilog and/or System Verilog. Our design activities are accomplished by a ... For example, Perl, TCL, C , Java, Verilog and System Verilog. Internship or...

LSI - Mendota Heights, MN

and mixed-signal circuits and systems; Verilog-AMS and wreal modeling experience ... including OVM/UVM verification flows and Verilog, SystemVerilog and Perl/Tcl languages...

Superior Group - Mendota Heights, MN

of SRAM and TCAM memory compilers in Verilog hardware description language.*The ... will have strong skills and experience in verilog coding and verification. ASIC or SoC...

Mindlance - Mendota Heights, MN

of SRAM and TCAM memory compilers in Verilog hardware description language. Skills ... will have strong skills and experience in verilog coding and verification. ASIC or SoC...

Seagate Technology - Shakopee, MN

* Designing in Verilog and/or System Verilog. * Our design activities are accomplished by a ... Perl, TCL, C++, Java, Verilog and System Verilog. * Internship or coursework...

QLogic - Shakopee, MN

review and understand complex RTL written in Verilog Strong analytical skills with ... Fluent in Verilog with exposure to System Verilog. Excellent written & verbal...

Micron Technology - Minneapolis, MN

verification languages (Verilog and System Verilog). * Familiarity with scripting languages (TCL, perl, Python) * Familiarity with industry standard verification methodology like...

Honeywell International - Minneapolis, MN

Interpret component datasheets and create VHDL/Verilog behavior models ... Ability to develop and simulate VHDL/Verilog models Experience with UNIX or Linux operatin...

LSI LOGIC - Mendota Heights, MN

and mixed-signal circuits and systems; Verilog-AMS and wreal modeling experience ... including OVM/UVM verification flows and Verilog, SystemVerilog and Perl/Tcl languages...