Top 88 Asic design memory controller Jobs

Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer
Qualcomm —San Diego, CA
- $140,000 - $210,000 a year
- Engineering
- Office
- 3 years
Lead Hardware Design Validation Engineer - Memory Subsystem
NVIDIA —Santa Clara, CA
- $168,000 - $322,000 a year
- Full-time
- Master's degree
- Scripting
- Linux
Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer
Qualcomm —San Diego, CA
- $140,000 - $210,000 a year
- Computer Science
- Engineering
- Mid-level
Senior Memory Controller Verification Engineer
NVIDIA —Santa Clara, CA
- $136,000 - $264,500 a year
- Full-time
- Hybrid work
- Software troubleshooting
- Bachelor of Science
- 3 years
Memory Subsystem Architect and Design Engineer
Advanced Micro Devices, Inc —Santa Clara, CA
- Hybrid work
- Analysis skills
- Product management
- Senior level
ASIC RTL Design Engineer, Interconnect & Memory Systems
Tesla —Palo Alto, CA
- $128,000 - $312,000 a year
- Full-time
- Computer science
- Computer Science
- 3 years
- Commuter assistance
- Health savings account
Design Verification Engineer
Intel —Santa Clara, CA
- $141,910 - $200,340 a year
- Full-time
- Hybrid work
- Computer Science
- Bachelor of Science
- Mid-level
- Health insurance
Staff Engineer, ASIC Design Verification
Samsung Semiconductor —San Jose, CA
- $163,000 - $253,000 a year
- Computer science
- Computer Science
- C++
Senior ASIC Design Engineer – Processor Subsystem
E-Space —Saratoga, CA
- $150,000 - $220,000 a year
- Weekends as needed
- 7 years
- Office
- Master's degree
- Paid holidays
- Paid time off
Distinguished Technologist, ASIC Design Architect
Hewlett Packard Enterprise —Sunnyvale, CA
- $183,000 - $389,500 a year
- Full-time
- 11+ years
- Office
- Master's degree
Memory Control Design Engineer
Qualcomm —San Diego, CA
- $115,600 - $173,400 a year
- Engineering
- Mid-level
- 3 years
Senior Principal Engineer Digital ASIC Design/Manager
Tubis Technology, Inc. —San Diego, CA
- $214,000 - $348,000 a year
- Online Application
- Bachelor of Science
- 11+ years
- Scripting
- Paid holidays
- Health insurance
Quick Apply
3D Memory Chip Architect and Design, Principal Engineer
Qualcomm —Hillsboro, OR
- $192,000 - $288,000 a year
- Computer science
- Computer Science
- Engineering
FPGA Design Engineer Sr
Lockheed Martin Corporation —Orlando, FL
- Full-time
- Bachelor of Science
- Mentoring
- Senior level
- Paid jury duty
- Paid holidays
Technical Director Memory Controller Architect
Rambus —San Jose, CA
- $189,700 - $352,300 a year
- Full-time
- Hybrid work
- Bachelor of Science
- System design
- 11+ years
- Employee stock purchase plan
- Health insurance
Senior Design Verification Engineer
Intel —Santa Clara, CA
- $164,470 - $311,890 a year
- Full-time
- Hybrid work
- Computer science
- Computer Science
- Bachelor of Science
- Health insurance
ASIC RTL Design Engineer, Ethernet IP & SoC Integration, AI Hardware
Tesla —Palo Alto, CA
- $128,000 - $312,000 a year
- Full-time
- 3 years
- Senior level
- Electrical Engineering
- Commuter assistance
- Health savings account
Senior ASIC Verification Engineer
NVIDIA —Santa Clara, CA
- $168,000 - $310,500 a year
- Full-time
- Computer Science
- Bachelor of Science
- 8 years
Senior Digital Design Engineer
FLC Technology Group —Santa Clara, CA
- Senior level
- Electrical Engineering
- 2 years
Senior Memory Subsystem Firmware Engineer
NVIDIA —Santa Clara, CA
- $152,000 - $241,500 a year
- Full-time
- Hybrid work
- Computer science
- Computer Science
- Bachelor of Science
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Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm -
San Diego, CA

Apply Now

Job Details

$140,000 - $210,000 a year

Benefits

Qualifications

Electronics design
System design for system development
Digital circuit design
Computer hardware
Design engineering

Full Job Description

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Job Description

Next Generation, High-Speed, Memory and Cache Controller and Advanced Memory NoCs based Subsystem Design Team is looking for a Senior ASIC Design Engineers for the next generation high speed HBM/LPDDR/DDR memory subsystems.. The front end of the DDR controller interfaces to the rest of the system such as CPU, GPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high speed (1Ghz+) designs in QCT products.

The candidate will work on architecture, design (RTL coding), and deployment of the next generation, high-speed memory subsystems into QCT products. You will develop or contribute to the development of architecture and design specifications and drive the micro-architecture of portions of the logic design. You will implement and deliver RTL and work with verification engineers to deliver high quality designs. You will be responsible for debugging your designs and also provide debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected to be key tasks. You will make regular contributions to the overall improvement in design methodology to drive productivity and quality of results.

Qualifications

Bachelor's or Masters degree in Science, Engineering, or related field.
5 + years ASIC design, RTL coding, front-end digital design experience
3+ years Hardware Architecture experience

Preferred Qualifications

3-10 years of ASIC design (RTL coding) Preferred
Exposure to RTL Design Verification flows is a plus
3+ years of direct Hardware Architecture experience
Bachelors degree in Electrical or Computer Engineering and at least 5+ years of experience in high speed digital design Master's degree preferred
Experience with the following:
LPDDR memory and cache controller, NoC based architectures especially the front end interfacing to the CPU, DSP, and multimedia processors
Exposure to HBM memory type designs
On-chip tightly coupled SRAM & L3 cache controller architecture/design
Experience with x86 or ARM CPU/bus architectures
Ordering of memory transactions and methods to enforce proper ordering in order to conform to ISA architecture specification

Education Requirements

Required: Bachelor's, Computer Engineering and/or Electrical Engineering
Preferred: Master's, Computer Engineering and/or Electrical Engineering

Minimum Qualifications:

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [email protected] or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range and Other Compensation & Benefits :

$140,000.00 - $210,000.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link .

If you would like more information about this role, please contact Qualcomm Careers .

Apply Now

Refine Your Search

asic design memory controller jobs

Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Lead Hardware Design Validation Engineer - Memory Subsystem

Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Senior Memory Controller Verification Engineer

Memory Subsystem Architect and Design Engineer

ASIC RTL Design Engineer, Interconnect & Memory Systems

Design Verification Engineer

Staff Engineer, ASIC Design Verification

Senior ASIC Design Engineer – Processor Subsystem

Distinguished Technologist, ASIC Design Architect

Memory Control Design Engineer

Senior Principal Engineer Digital ASIC Design/Manager

3D Memory Chip Architect and Design, Principal Engineer

FPGA Design Engineer Sr

Technical Director Memory Controller Architect

Senior Design Verification Engineer

ASIC RTL Design Engineer, Ethernet IP & SoC Integration, AI Hardware

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Senior Digital Design Engineer

Senior Memory Subsystem Firmware Engineer

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