Top 94 Asic design memory controller Jobs

ASIC RTL Design Engineer, Interconnect & Memory Systems
Tesla —Palo Alto, CA
- $128,000 - $312,000 a year
- Full-time
- Computer science
- Computer Science
- 3 years
- Commuter assistance
- Health savings account
Senior ASIC Design Engineer – Processor Subsystem
E-Space —Saratoga, CA
- $150,000 - $220,000 a year
- Weekends as needed
- 7 years
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3D Memory Chip Architect and Design, Principal Engineer
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Lead Hardware Design Validation Engineer - Memory Subsystem
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Memory Control Design Engineer
Qualcomm —San Diego, CA
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Senior Principal Engineer Digital ASIC Design/Manager
Tubis Technology, Inc. —San Diego, CA
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- Online Application
- Bachelor of Science
- 11+ years
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Quick Apply
Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer
Qualcomm —San Diego, CA
- $140,000 - $210,000 a year
- Engineering
- Office
- 3 years
Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer
Qualcomm —San Diego, CA
- $140,000 - $210,000 a year
- Computer Science
- Engineering
- Mid-level
Senior Memory Controller Verification Engineer
NVIDIA —Santa Clara, CA
- $136,000 - $264,500 a year
- Full-time
- Hybrid work
- Software troubleshooting
- Bachelor of Science
- 3 years
Senior Digital Design Engineer
FLC Technology Group —Santa Clara, CA
- Senior level
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- 2 years
Distinguished Technologist, ASIC Design Architect
Hewlett Packard Enterprise —Westford, MA
- $183,000 - $389,500 a year
- Full-time
- 11+ years
- Office
- Master's degree
Staff Engineer, ASIC Design Verification
Samsung Semiconductor —San Jose, CA
- $163,000 - $253,000 a year
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- Computer Science
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Technical Director Memory Controller Architect
Rambus —San Jose, CA
- $189,700 - $352,300 a year
- Full-time
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- Bachelor of Science
- System design
- 11+ years
- Employee stock purchase plan
- Health insurance
Senior Design Engineer
FLC Technology Group —Santa Clara, CA
- Master's degree
- Senior level
- Electrical Engineering
ASIC Design Verification Engineer, Platforms and Devices
Google —Mountain View, CA
- $138,000 - $198,000 a year
- Full-time
- Computer science
- Computer Science
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FPGA Design Engineer
Normal Computing Corporation —New York, NY
- $200,000 - $280,000 a year
- Full-time
- Hybrid work
- C++
- Senior level
- Python
11d
Memory Subsystem Architect and Design Engineer
Advanced Micro Devices, Inc —Santa Clara, CA
- Hybrid work
- Analysis skills
- Product management
- Senior level
ASIC RTL Design Engineer, Ethernet IP & SoC Integration, AI Hardware
Tesla —Palo Alto, CA
- $128,000 - $312,000 a year
- Full-time
- 3 years
- Senior level
- Electrical Engineering
- Commuter assistance
- Health savings account
Formal Verification - DV
Etched —San Jose, CA
- Full-time
- 5 years
- Office
- Senior level
- Health insurance
- Dental insurance
Hardware Design Engineer
Rambus —Hillsboro, OR
- $106,900 - $198,500 a year
- Full-time
- Hybrid work
- 5 years
- System design
- Office
- Employee stock purchase plan
- Health insurance

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ASIC RTL Design Engineer, Interconnect & Memory Systems

Tesla -
Palo Alto, CA

Apply Now

Job Details

Full-time
$128,000 - $312,000 a year

Benefits

Commuter assistance
Health savings account
AD&D insurance
Paid holidays
Disability insurance
Health insurance
Dental insurance
Flexible spending account
Flextime
Adoption assistance
Employee assistance program
401(k) matching
Employee discount
Benefits from day one
Pet insurance

Qualifications

QoS
Network design
Engineering development testing
Automation
Tooling
Electronics design
SoC
Digital circuit design
Cross-functional communication

Full Job Description

What to Expect

The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.

The Tesla AI Hardware team is looking for an ASIC RTL Design Engineer specializing in interconnect and memory systems to drive the development of next-generation AI accelerators. In this role, you will focus on the critical data path elements of custom ASICs, including Network on Chip (NoC) architectures, DMA engines, memory controllers, Memory Management Units (MMUs), arbiters, and AXI protocol implementations. You will collaborate closely with system architects, verification engineers, physical design teams, and software/firmware developers to deliver high-performance, power-efficient designs that enable massive-scale AI training and inference. This position is based in Palo Alto, CA, or Austin, TX and offers the opportunity to work on cutting-edge hardware that powers Tesla's autonomous driving and AI initiatives.

What You'll Do

Architect, design, and implement RTL (Verilog/SystemVerilog) for high-performance interconnect and memory subsystems, including NoC topologies, DMA controllers, and AXI-based data paths optimized for AI workloads
Develop and document microarchitecture specifications for memory controllers, MMUs, and arbiters to ensure low-latency, high-bandwidth data movement across SoC components
Define system-level functional requirements for SoC data paths, focusing on throughput, scalability, and integration with compute accelerators
Perform design analysis, including timing closure, power optimization, and area efficiency, for high-performance memory and interconnect blocks
Collaborate with cross-functional teams to integrate interconnect IP into full-chip designs, debug issues, and support silicon bring-up and validation
Contribute to performance modeling and simulation of data path elements to meet aggressive AI hardware metrics
Stay abreast of industry trends in high-performance ASIC design and propose innovations for interconnect and memory efficiency

What You'll Bring

Degree in Electrical Engineering, Computer Science, or equivalent experience
3+ years of hands-on RTL design experience in SoC interconnect, memory systems, or data path components for custom ASICs
Strong proficiency in Verilog or SystemVerilog for complex digital design
Solid understanding of AXI protocol and high-performance design techniques (e.g., pipelining, clock domain crossing)
Experience with synthesis, timing analysis, and linting tools (e.g., Synopsys Design Compiler, SpyGlass)
Ability to work in a fast-paced, collaborative environment with strong problem-solving skills
Proven track record in Network on Chip (NoC) design, including topology selection, routing algorithms, and QoS mechanisms
Deep expertise in DMA engine design, memory controller architectures (e.g., DDR/LPDDR interfaces), MMUs, and priority arbiters for multi-master systems
Experience with high-performance SoC data path optimization for AI/ML accelerators or HPC applications
Familiarity with verification methodologies (e.g., UVM) and scripting (Python/Perl) for automation

Compensation and Benefits

Benefits

Along with competitive pay, as a full-time Tesla employee, you are eligible for the following benefits at day 1 of hire:

Medical plans > plan options with $0 payroll deduction
Family-building, fertility, adoption and surrogacy benefits
Dental (including orthodontic coverage) and vision plans, both have options with a $0 paycheck contribution
Company Paid (Health Savings Accounts) HSA Contribution when enrolled in the High-Deductible medical plan with HSA
Healthcare and Dependent Care Flexible Spending Accounts (FSA)
401(k) with employer match, Employee Stock Purchase Plans, and other financial benefits
Company paid Basic Life, AD&D
Short-term and long-term disability insurance (90 day waiting period)
Employee Assistance Program
Sick and Vacation time (Flex time for salary positions, Accrued hours for Hourly positions), and Paid Holidays
Back-up childcare and parenting support resources
Voluntary benefits to include: critical illness, hospital indemnity, accident insurance, theft & legal services, and pet insurance
Weight Loss and Tobacco Cessation Programs
Tesla Babies program
Commuter benefits
Employee discounts and perks program

Expected Compensation

$128,000 - $312,000/annual salary + cash and stock awards + benefits

Pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. The total compensation package for this position may also include other elements dependent on the position offered. Details of participation in these benefit plans will be provided if an employee receives an offer of employment.

Tesla is an Equal Opportunity / Affirmative Action employer committed to diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state or local laws.

Tesla is also committed to working with and providing reasonable accommodations to individuals with disabilities. Please let your recruiter know if you need an accommodation at any point during the interview process.

Apply Now

Refine Your Search

asic design memory controller jobs

ASIC RTL Design Engineer, Interconnect & Memory Systems

Senior ASIC Design Engineer – Processor Subsystem

3D Memory Chip Architect and Design, Principal Engineer

Lead Hardware Design Validation Engineer - Memory Subsystem

Memory Control Design Engineer

Senior Principal Engineer Digital ASIC Design/Manager

Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Senior Memory Controller Verification Engineer

Senior Digital Design Engineer

Distinguished Technologist, ASIC Design Architect

Staff Engineer, ASIC Design Verification

Technical Director Memory Controller Architect

Senior Design Engineer

ASIC Design Verification Engineer, Platforms and Devices

FPGA Design Engineer

Memory Subsystem Architect and Design Engineer

ASIC RTL Design Engineer, Ethernet IP & SoC Integration, AI Hardware

Formal Verification - DV

Hardware Design Engineer

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