Top 76 Asic design memory controller Jobs

Principal ASIC Architect - Memory Systems & AI Interconnects
Everforth —South Boston, MA
- $200,000 - $300,000 a year
- Full-time
- Computer Science
- System design
- Doctor of Philosophy
- Relocation assistance
- Health insurance
10d
Memory Control Design Engineer
Qualcomm —San Diego, CA
- $115,600 - $173,400 a year
- Engineering
- Mid-level
- 3 years
Distinguished Technologist, ASIC Design Architect
Hewlett Packard Enterprise —Westford, MA
- $183,000 - $389,500 a year
- Full-time
- 11+ years
- Office
- Master's degree
Senior ASIC Design Engineer
NVIDIA —Santa Clara, CA
- $136,000 - $264,500 a year
- Full-time
- Hybrid work
- Computer science
- Computer Science
- 5 years
3d
Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer
Qualcomm —San Diego, CA
- $140,000 - $210,000 a year
- Computer Science
- Engineering
- Mid-level
Technical Director Memory Controller Architect
Rambus —San Jose, CA
- $189,700 - $352,300 a year
- Full-time
- Hybrid work
- Bachelor of Science
- System design
- 11+ years
- Employee stock purchase plan
- Health insurance
Staff Engineer, ASIC Design Verification
Samsung Semiconductor —San Jose, CA
- $163,000 - $253,000 a year
- Computer science
- Computer Science
- C++
3D Memory Chip Architect and Design, Principal Engineer
Qualcomm —Hillsboro, OR
- $192,000 - $288,000 a year
- Computer science
- Computer Science
- Engineering
Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer
Qualcomm —San Diego, CA
- $140,000 - $210,000 a year
- Engineering
- Office
- 3 years
Hardware Design Engineer
Rambus —Hillsboro, OR
- $106,900 - $198,500 a year
- Full-time
- Hybrid work
- 5 years
- System design
- Office
- Employee stock purchase plan
- Health insurance
Senior Memory Controller Verification Engineer
NVIDIA —Santa Clara, CA
- $136,000 - $264,500 a year
- Full-time
- Hybrid work
- Software troubleshooting
- Bachelor of Science
- 3 years
Lead Hardware Design Validation Engineer - Memory Subsystem
NVIDIA —Santa Clara, CA
- $168,000 - $322,000 a year
- Full-time
- Master's degree
- Scripting
- Linux
Senior ASIC Design Engineer – Processor Subsystem
E-Space —Saratoga, CA
- $150,000 - $220,000 a year
- Weekends as needed
- 7 years
- Office
- Master's degree
- Paid holidays
- Paid time off
Memory Subsystem Architect and Design Engineer
Advanced Micro Devices, Inc —Santa Clara, CA
- Hybrid work
- Analysis skills
- Product management
- Senior level
ASIC RTL Design Engineer, Interconnect & Memory Systems
Tesla —Palo Alto, CA
- $128,000 - $312,000 a year
- Full-time
- Computer science
- Computer Science
- 3 years
- Commuter assistance
- Health savings account
Technical Director PCIe Controller Architect
Rambus —San Jose, CA
- $189,700 - $352,300 a year
- Full-time
- Hybrid work
- Bachelor of Science
- 11+ years
- Office
- Employee stock purchase plan
- Health insurance
Sr. Digital ASIC Engineer
Skyworks Solutions —Hillsboro, OR
- $91,200 - $177,200 a year
- Doctor of Philosophy
- Senior level
- Electrical Engineering
- Employee stock purchase plan
- Health insurance
Principal Logic Design Engineer
Rambus —Hillsboro, OR
- $127,400 - $236,600 a year
- Full-time
- Hybrid work
- Office
- Master's degree
- 8 years
- Employee stock purchase plan
- Health insurance
Senior ASIC Verification Engineer
NVIDIA —Santa Clara, CA
- $168,000 - $310,500 a year
- Full-time
- Computer Science
- Bachelor of Science
- 8 years
Principal Engineer, ASIC Physical Design
Micron —Minneapolis, MN
- Master's degree
- Analysis skills
- Experience equivalent to degree accepted
- Employee stock purchase plan
- Paid holidays

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Principal ASIC Architect - Memory Systems & AI Interconnects

Everforth -
South Boston, MA

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Job Details

Full-time
$200,000 - $300,000 a year
10 days ago

Benefits

Visa sponsorship
Relocation assistance
Health insurance
Dental insurance
Vision insurance
401(k) matching
Life insurance

Qualifications

Data caching
SoC
Digital circuit design
Design engineering
ARM

Full Job Description

Principal ASIC Architect - Memory Systems & AI Interconnects

Job Title: Principal ASIC Architect - Memory Systems & AI Interconnects
Job Location: Santa Clara, CA or Boston, MA
Compensation: $200K - $300K plus bonus and equity
Requirements: ASIC Architecture, Memory Subsystems, CXL / NVLink / PCIe / UCIe/ UALink / RDMA, ARM CHI, AI Accelerators

Our company is working on solving the memory wall for AI. We develop memory-to-compute networking solutions for AI infrastructure, with a focus on high-bandwidth optical interconnects for XPU memory expansion.

Position Overview
We are seeking a Principal ASIC Architect to lead architecture and system-level design of memory subsystems and AI interconnects for next-generation AI accelerators and SoCs. The role combines deep expertise in memory systems architecture, interconnect protocols (CXL, NVLink, UALink, RDMA, ARM CHI, UCIe, PCIe), and performance modeling to define high-bandwidth, low-latency solutions that scale across accelerator, host, and memory fabrics. You will partner with product teams, ASIC design, verification, firmware, and system integration to set architectural direction, drive technical tradeoffs, and ensure robust, high-performance solutions for ML hardware and AI workloads.

Key Responsibilities

Define end-to-end memory and interconnect architectures for AI accelerators, including coherent and non-coherent fabrics, memory pooling, and tiered memory hierarchies.
Lead specification and micro-architecture of interfaces and protocols (CXL, NVLink, UALink, RDMA, UCIe, PCIe, ARM CHI) and their integration into SoC designs and AI accelerators.
Develop performance, latency, and bandwidth models and run system-level simulations to evaluate architectural trade-offs and inform design decisions.
Collaborate with RTL, verification, firmware, and physical design teams to translate architecture into implementable hardware blocks and ensure design-for-performance.
Drive cross-functional reviews with product management, systems teams, and external IP partners to align on interfaces, compliance, and interoperability.
Architect solutions for memory subsystems including HBM, DDR, persistent memory, and CXL-attached devices, optimizing for AI/ML workloads and data movement patterns.
Define verification and validation strategies for interconnect and memory subsystems, including test plans for coherence, error handling, flow control, and performance stress tests.
Mentor and lead other architects and engineers, setting best practices, architectural patterns, and documentation for memory and interconnect subsystems.
Keep abreast of industry trends, emerging protocols, and ecosystem developments; represent the company in standards and partner engagements as needed.
Provide technical leadership during silicon bring-up, performance tuning, and system-level debugging to achieve target performance and reliability metrics.

Qualifications

Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science or related field; MS or PhD preferred.
10+ years of experience in ASIC/SoC architecture, with a significant focus on memory systems and interconnects for high-performance computing or AI.
Deep working knowledge of CXL, NVLink, UALink, RDMA, ARM CHI, UCIe, and PCIe protocols and how they are used to build coherent and high-performance systems.
Experience with memory subsystems (HBM, DDR, persistent memory), memory controller architecture, cache coherency and memory consistency models.
Hands-on experience with AI accelerators, ML hardware architectures, dataflow characteristics of ML workloads, and integration of accelerators into SoCs.
Strong background in performance modeling, system-level simulation, and latency/bandwidth analysis.
Familiarity with RTL design concepts, verification methodologies, and silicon bring-up processes; ability to review microarchitecture and RTL for performance implications.
Excellent written and verbal communication skills; proven ability to collaborate across teams and influence technical decisions.
Proven track record of technical leadership, mentoring engineers, and delivering complex ASIC/SoC projects on schedule.

#Enghp

Benefits

Competitive salary commensurate with experience including base salary, performance-based bonus, and early-stage equity grant
Comprehensive benefits including health, dental, vision, and life insurance
Well-equipped, sunny offices in Santa Clara, CA and Boston, MA
Relocation assistance and visa sponsorship
Perks include a daily lunch stipend, 401k match, and more
A collaborative, continuous-learning work environment with smart, dedicated colleagues engaged in developing the next generation of architecture for high-performance computing
For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. This job was first posted by CyberCoders on 07/18/2026 and applications will be accepted on an ongoing basis until the position is filled or closed.Everforth CyberCoders is proud to be an Equal Opportunity Employer

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter . Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at [email protected] to make arrangements.

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Refine Your Search

asic design memory controller jobs

Principal ASIC Architect - Memory Systems & AI Interconnects

Memory Control Design Engineer

Distinguished Technologist, ASIC Design Architect

Senior ASIC Design Engineer

Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Technical Director Memory Controller Architect

Staff Engineer, ASIC Design Verification

3D Memory Chip Architect and Design, Principal Engineer

Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Hardware Design Engineer

Senior Memory Controller Verification Engineer

Lead Hardware Design Validation Engineer - Memory Subsystem

Senior ASIC Design Engineer – Processor Subsystem

Memory Subsystem Architect and Design Engineer

ASIC RTL Design Engineer, Interconnect & Memory Systems

Technical Director PCIe Controller Architect

Sr. Digital ASIC Engineer

Principal Logic Design Engineer

Senior ASIC Verification Engineer

Principal Engineer, ASIC Physical Design

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