Top 1969 Asic engineer Jobs

Lead ASIC DFT Engineer
Cyient —Remote
- From $100 an hour
- Full-time
- Remote
- Analysis skills
- Mentoring
- Senior level
Quick Apply
ASIC Design Verification Engineer
Positron AI —Remote
- $200,000 - $350,000 a year
- Full-time
- Remote
- Master's degree
- 8 years
- Analysis skills
Quick Apply
ASIC Clocks Verification Engineer - New College Grad 2026
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- Hybrid work
- Mid-level
- Master's degree
- Experience equivalent to degree accepted
ASIC Verification Engineer - New College Grad 2026
NVIDIA —Austin, TX
- $100,000 - $189,750 a year
- Full-time
- Computer science
- Computer Science
- Bachelor of Science
Lead ASIC DFT Engineer
ZK Technologies —Remote
- $115,496.06 - $139,092.03 a year
- Contract
- Remote
- Analysis skills
- Mentoring
- Senior level
Quick Apply
Low Power ASIC Engineer - New College Grad 2026
NVIDIA —Santa Clara, CA
- $100,000 - $189,750 a year
- Full-time
- Bachelor of Science
- Doctor of Philosophy
- Electrical Engineering
ASIC Clocks Design Engineer - New College Grad 2026
NVIDIA —Austin, TX
- $100,000 - $189,750 a year
- Full-time
- Mid-level
- Electrical Engineering
ASIC Validation Engineer
Block, Inc. —San Francisco Bay Area, CA
- $139,000 - $245,400 a year
- Remote
- Mid-level
- Travel
- Fair chance
- Life insurance
- Retirement plan
ASIC Verification Engineer
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- Computer science
- Computer Science
- Research
Engineer In Training (EIT)
Infinity Engineering, LLC —Franklin, TN
- $75,000 - $90,000 a year
- Full-time
- Office
- Microsoft Office
- Analysis skills
- Wellness program
- Mileage reimbursement
Quick Apply
10h
FPGA Design Manager / Section Lead
BAE Systems Inc. —Totowa, NJ
- $153,377 - $260,743 a year
- Full-time
- Hybrid work
- Microsoft Word
- Computer Science
- Master's degree
- Health savings account
- Paid holidays
Lead ASIC DFT Engineer
Cyient —San Jose, CA
- $80 - $85 an hour
- Full-time
- Analysis skills
- Mentoring
- In-person
Quick Apply
Senior FPGA / ASIC Design Assurance Engineer
Cyient —Melbourne, FL
- $101,037.27 - $121,679.30 a year
- Full-time
- Background check
- Computer Science
- 8 years
- Health savings account
- Relocation assistance
Quick Apply
5d
Physical Design Engineer
iTechStack Inc. —Mountain View, CA
- $110,000 - $150,000 a year
- Full-time
- Mid-level
- Master's degree
- In-person
- Health insurance
- Dental insurance
Quick Apply
13d
Senior Electrical Engineer - ASIC/FPGA Verification (Onsite)
Collins Aerospace —Cedar Rapids, IA
- $86,800 - $165,200 a year
- Full-time
- 3 years
- Scripting
- In-person
- Paid holidays
- Loan repayment program
12d
Static Timing Analysis Engineer
iTechStack Inc. —San Jose, CA
- $100,000 - $150,000 a year
- Full-time
- 3 years
- Master's degree
- Bachelor's degree
Quick Apply
13d
Advanced ASIC FPGA Design Engineer for Crypto and Cross Domain Solutions
General Dynamics Mission Systems, Inc —Scottsdale, AZ
- $135,396 - $150,205 a year
- Full-time
- 3 years
- Master's degree
- Analysis skills
Lead ASIC Digital Design Engineer
General Dynamics Mission Systems, Inc —Annapolis Junction, MD
- $176,512 - $187,000 a year
- Full-time
- Hybrid work
- 5 years
- Master's degree
- Analysis skills
FPGA Engineer
Cyient —Melbourne, FL
- $110,000 - $140,000 a year
- Full-time
- 5 years
- In-person
- Senior level
- Relocation assistance
- Health insurance
Quick Apply
Advanced ASIC FPGA Engineer
General Dynamics Mission Systems, Inc —Pittsfield, MA
- $128,854 - $142,947 a year
- Full-time
- Data analysis skills
- Research
- 3 years

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Lead ASIC DFT Engineer

Cyient -
Remote

Quick Apply

Job Details

Full-time | Contract
From $100 an hour

Qualifications

Engineering development testing
Electronics functional testing
Integrated circuits (ICs)
Analysis skills
SoC
Digital circuit design
Product development
System architecture design
Simulation tools
Test analysis
Python
Debugging
Cross-functional communication

Full Job Description

Experience

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
Act as a technical escalation point for advanced DFT and post-silicon debug issues.
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

Strong hands-on experience in ASIC DFT with end-to-end ownership.
Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
Experience with MBIST implementation and verification; SMS experience preferred.
Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
Proven post-silicon debug and silicon bring-up experience.
Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

MBIST post-silicon validation.
ATPG simulations and fault coverage debug.
DFT RTL, DFD, DFT verification, and IP-level DFT integration.
DFT SDC creation and DFT timing closure support.
Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
TCL/PERL scripting for DFT automation, reporting, and debug.
Experience working across multiple ASIC technology nodes and complex product development cycles.
Familiarity with yield learning, diagnosis, and manufacturing test optimization.

Pay: From $100.00 per hour

Work Location: Remote

Quick Apply

Refine Your Search

asic engineer jobs

Lead ASIC DFT Engineer

ASIC Design Verification Engineer

ASIC Clocks Verification Engineer - New College Grad 2026

ASIC Verification Engineer - New College Grad 2026

Lead ASIC DFT Engineer

Low Power ASIC Engineer - New College Grad 2026

ASIC Clocks Design Engineer - New College Grad 2026

ASIC Validation Engineer

ASIC Verification Engineer

Engineer In Training (EIT)

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Lead ASIC DFT Engineer

Senior FPGA / ASIC Design Assurance Engineer

Physical Design Engineer

Senior Electrical Engineer - ASIC/FPGA Verification (Onsite)

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Advanced ASIC FPGA Design Engineer for Crypto and Cross Domain Solutions

Lead ASIC Digital Design Engineer

FPGA Engineer

Advanced ASIC FPGA Engineer

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