Top 152 Cisco network design engineer Jobs

ASIC Design Verification Engineer, Technical Leader
Cisco Systems —San Jose, CA
- $163,600 - $303,100 a year
- Full-time
- Office
- Master's degree
- 8 years
- Paid parental leave
- Paid holidays
ASIC Physical Design Principal Engineer
Cisco Systems —San Jose, CA
- $222,900 - $381,600 a year
- Full-time
- 7 years
- Engineering
- Analysis skills
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ASIC Design Verification Engineer
Cisco Systems —San Jose, CA
- $135,800 - $252,000 a year
- Full-time
- Computer science
- Computer Science
- Master's degree
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Package Mechanical Design Engineer
Cisco Systems —San Jose, CA
- $146,700 - $277,600 a year
- Full-time
- Master's degree
- Analysis skills
- Doctor of Philosophy
- Paid parental leave
- Paid holidays
ASIC Design Engineer, STA
Cisco Systems —San Jose, CA
- $135,800 - $252,000 a year
- Full-time
- Office
- Master's degree
- Doctor of Philosophy
- Paid parental leave
- Paid holidays
ASIC Design Verification Engineer
Cisco Systems —San Jose, CA
- $146,700 - $277,600 a year
- Full-time
- Computer science
- Computer Science
- Master's degree
- Paid parental leave
- Paid holidays
Design Verification Engineer - Acacia Networks
Cisco Systems —Holmdel, NJ
- $134,300 - $255,100 a year
- Full-time
- Laboratory experience
- Master's degree
- C++
- Paid parental leave
- Paid holidays
Physical Design Engineer
Cisco Systems —San Jose, CA
- $146,700 - $277,600 a year
- Full-time
- Master's degree
- Analysis skills
- Doctor of Philosophy
- Paid parental leave
- Paid holidays
ASIC Design Verification Emulation Engineer
Cisco Systems —San Jose, CA
- $146,700 - $277,600 a year
- Full-time
- Master's degree
- Bachelor's degree
- Doctor of Philosophy
- Paid parental leave
- Paid holidays
Cloud Engineer
Cisco Systems —Research Triangle Park, NC
- $126,500 - $252,000 a year
- Full-time
- Hybrid work
- Azure
- Computer Science
- 5 years
- Paid parental leave
- Paid holidays
Senior ASIC Physical Design Engineer
Cisco Systems —San Jose, CA
- $146,700 - $277,600 a year
- Full-time
- Master's degree
- Analysis skills
- Doctor of Philosophy
- Paid parental leave
- Paid holidays
ASIC Design Verfication Engineer II (Full Time) - United States
Cisco Systems —San Jose, CA
- $109,900 - $200,100 a year
- Full-time
- Mid-level
- Master's degree
- Bachelor's degree
- Paid parental leave
- Paid holidays
Hardware Design Engineer Technical Lead
Cisco Systems —San Jose, CA
- $148,800 - $277,400 a year
- Full-time
- 6 years
- Master's degree
- Doctor of Philosophy
- Paid parental leave
- Paid holidays
Principal Machine Learning Engineer
Cisco Systems —San Jose, CA
- $259,400 - $424,400 a year
- Full-time
- Remote
- 7 years
- Computer Science
- Research
- Paid parental leave
- Paid holidays
Software Engineer, Information Experience
Cisco Systems —Research Triangle Park, NC
- $126,500 - $252,000 a year
- Full-time
- Remote
- Azure
- 3 years
- Master's degree
- Paid parental leave
- Paid holidays
Silicon Photonics Senior Design Engineer- (Hybrid)
Cisco Systems —Carlsbad, CA
- $134,300 - $255,100 a year
- Full-time
- Hybrid work
- Office
- Master's degree
- Doctor of Philosophy
- Paid parental leave
- Paid holidays
Hardware Design Engineer
Cisco Systems —Milpitas, CA
- $122,000 - $222,400 a year
- Full-time
- Writing skills
- Office
- 3 years
- Paid parental leave
- Paid holidays
ASIC Design Verification Technical Leader
Cisco Systems —Carlsbad, CA
- $163,600 - $303,100 a year
- Full-time
- 3 years
- Master's degree
- Continuous improvement
- Paid parental leave
- Paid holidays
Technical Leader- Quantum Networking Hardware Engineer
Cisco Systems —Santa Monica, CA
- $163,600 - $303,100 a year
- Full-time
- Computer Science
- Doctor of Philosophy
- US work authorization
- Paid parental leave
- Paid holidays
Hardware Engineer
Cisco Systems —Milpitas, CA
- $122,000 - $222,400 a year
- Full-time
- Mid-level
- Master's degree
- Doctor of Philosophy
- Paid parental leave
- Paid holidays

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ASIC Design Verification Engineer, Technical Leader

Cisco Systems -
San Jose, CA

Apply Now

Job Details

Full-time
$163,600 - $303,100 a year

Benefits

Paid parental leave
Paid holidays
Disability insurance
Health insurance
Dental insurance
401(k)
RSU
Parental leave
Vision insurance
401(k) matching
Life insurance

Qualifications

Engineering development testing
Verification (System development task)
SystemVerilog

Full Job Description

The application window is expected to close on: 07/31/2026Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

This role will work onsite out of our San Jose, CA office.

Who We Are:
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Who You'll Work With:
You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification engineers, designers, hardware and cross-functional teams to verify the ASIC in simulation, in emulation, and during ASIC bring-up.

What You'll Do:

Maintaining existing DV environments and enhancing them
Construct test bench including scoreboard, agents, sequencers, and monitors for new blocks
Write test plan, develop test cases, debug regression failures and drive to module verification closure
Ensuring complete verification coverage through implementation and review of code and functional coverage
Use AI tools to develop innovative methods and processes to improve quality of design verification.

Minimum Qualifications:

Bachelor's with 8+ years or Master's degree with 6+ of relevant experience required; prior experience with System Verilog and UVM methodology
Prior experience in verifying complex blocks, cluster, and/or top level for ASIC/SoC
Prior experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
Prior experience with functional coverage and constrained random DV environments.
Scripting skills: Perl and/or Python scripting

Preferred Qualifications:

Strong domain experience in one or more protocols is a plus – PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU.
Experience with Veloce/HAPS is a plus
Formal verification (iev/vc formal) knowledge is a plus

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $183,800.00 to $263,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and
Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:
$183,800.00 - $303,100.00

Non-Metro New York state& Washington state:
$163,600.00 - $269,800.00

For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

Apply Now

Refine Your Search

cisco network design engineer jobs

ASIC Design Verification Engineer, Technical Leader

ASIC Physical Design Principal Engineer

ASIC Design Verification Engineer

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ASIC Design Engineer, STA

ASIC Design Verification Engineer

Design Verification Engineer - Acacia Networks

Physical Design Engineer

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Senior ASIC Physical Design Engineer

ASIC Design Verfication Engineer II (Full Time) - United States

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Software Engineer, Information Experience

Silicon Photonics Senior Design Engineer- (Hybrid)

Hardware Design Engineer

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Technical Leader- Quantum Networking Hardware Engineer

Hardware Engineer

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