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THW Client Co-op

Ciena -
New York, NY

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Job Details

Full-time
$27.00 - $37.50 an hour

Benefits

Paid holidays
Employee assistance program
Paid sick time

Qualifications

Content creation for technical audiences
Technical documentation
VHDL
Verilog
Technical writing experience within technology
Python

Full Job Description

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

The Opportunity: 4 month work term (Aug/Sept - Dec, 2026)

How You Will Contribute:

As a successful candidate, you will be working within the ASIC IP team with other design and verification engineers, performing digital ASIC design and verification of the Client sub-systems and cores.

The Client team crafts, develops, and tests the client protocol mapping IP of Ciena’s industry leading Wavelogic coherent engine Chipsets. Wavelogic ASICs are widely used in Ciena products, and they are one of the main contributors to Ciena’s success.

During your coop term in our team, you will learn about many aspects of the digital ASIC development such as our design and verification environment, prototype development, and development automation. You will be assigned well defined tasks that will allow you to contribute to our team and broaden your knowledge and gain experience in optical networking and digital ASIC development.

RTL design and verification of digital blocks, cores, and subsystems for ASIC products and FPGA-based validation. You will gain in-depth knowledge of many communications standards from IEEE 802.3, ITU, and OIF, as well as understanding system wide concepts.

Work as a team member that is responsible for the design and verification of complex digital blocks and subsystems

Implement and verify digital designs using System Verilog/UVM

The Must Haves:

Good academic standing in a Bachelor’s degree program in Electrical Engineering or Computer Engineering

Previous experience with ASIC or FPGA development, as well as knowledge of and experience using System Verilog, Verilog, VHDL and Python

Strong verbal and technical writing skills

Self-motivated, and the ability to work independently as well as in a team environment

Assets:

Knowledge of OTN, Ethernet, and other Optical Networking standards

Strong problem solving and debugging skills

Experience working in a Linux environment

Pay Range:

The hourly pay range for this position is $27.00 - $37.50

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

In addition to competitive compensation, Ciena offers students access to the Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation pay as required by applicable laws.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

Apply Now

Refine Your Search

client technologies co op jobs

THW Client Co-op

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