Top 26943 Design/verification engineer Jobs

Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions
General Dynamics Mission Systems, Inc —Scottsdale, AZ
- $135,396 - $150,205 a year
- Full-time
- 3 years
- Master's degree
- Analysis skills
Software Engineer - Avionics RF Design and Integration
Capgemini —Atlanta, GA
- $79,750 - $159,500 a year
- Full-time
- Senior level
- Python
- Paid holidays
- Disability insurance
11d
Software Engineer - Avionics RF Design and Integration
Capgemini —Seattle, WA
- $79,750 - $174,000 a year
- Full-time
- Senior level
- Python
- Paid holidays
- Disability insurance
11d
RF Design Engineer
Wilson Connectivity —Dallas, TX
- $100,000 - $110,000 a year
- Full-time
- Microsoft Excel
- Microsoft Outlook
- Computer literacy
Quick Apply
Principal Design Verification Engineer - PCIe / High-Speed SoC
Everforth —Santa Clara, CA
- $200,000 - $250,000 a year
- Full-time
- Management
- Analysis skills
- C++
- Employee stock purchase plan
- Paid holidays
10d
Verification Engineer - Aeromechanical (Design & Test)
Pivotal —Palo Alto, CA
- $115,000 - $145,000 a year
- Full-time
- Writing skills
- Mid-level
- Master's degree
- Health insurance
- Dental insurance
Quick Apply
MLA Design Verification Engineer I, Annapurna Labs
Amazon.com Services LLC —Austin, TX
- $109,700 - $160,000 a year
- Full-time
- Software development experience
- 1 year
- Electrical Engineering
- AD&D insurance
- Health insurance
Design Verification Engineer II
Forj Medical —Saint Paul, MN
- $75,000 - $95,000 a year
- Full-time
- Bachelor of Science
- Data analysis skills
- Laboratory experience
- Dental insurance
- 401(k)
Quick Apply
Circuit Design Engineer - New College Grad 2026
NVIDIA —Santa Clara, CA
- $116,000 - $189,750 a year
- Full-time
- Data analysis skills
- Analysis skills
- Software development experience
Design Verification Engineer
Insilico —Irvine, CA
- Contract
- Senior level
Quick Apply
ASIC design/verification engineer
Hewlett Packard Enterprise —Durham, NC
- $135,000 - $310,500 a year
- Full-time
- 6 years
- English
- Office
SLD FPGA Verification Engineer III - Lunar Permanence
Blue Origin —Seattle, WA
- $130,706.00 - $182,987.70 a year
- Full-time
- Background check
- 5 years
- Bachelor of Science
- Paid parental leave
- Paid holidays
Digital Design Verification Engineer (AZ)
Talent 101 Inc —Tucson, AZ
- $0 a year
- Full-time
- Background check
- 18 years or older
- Pass drug screening
Quick Apply
ASIC/FPGA Design Verification Engineer
Teradyne —North Reading, MA
- $123,100 - $196,900 a year
- 5 years
- Office
- Senior level
- Paid holidays
- Disability insurance
Sr Design Verification Engineer
Ventana Micro Systems —Austin, TX
- Full-time
- 8 years
- Senior level
- Python
Entry Level Digital Design Engineer, Carlisle, MA
Assurance Technology Corporation (ATC) —Carlisle, MA
- $80,000 - $95,000 a year
- Full-time
- Bachelor of Science
- System design
- Electrical Engineering
Quick Apply
ASIC Physical Design Engineer, Netlisting - New College Grad 2026
NVIDIA —Austin, TX
- $116,000 - $218,500 a year
- Full-time
- Mid-level
- Doctor of Philosophy
- Experience equivalent to degree accepted
Senior Design Verification Engineer (eInfochips Inc)
Arrow Electronics, Inc. —Eden Prairie, MN
- Full-time
- Office
- Master's degree
- Travel
- Health savings account
- Paid holidays
Test Engineer I - Early Career (2026 Starts)
Blue Origin —Florida
- Background check
- Bachelor of Science
- DOT physical examination
- Paid parental leave
- Paid holidays
R&D Engineer III, 3D Printing Design
Align Technology —San Jose, CA
- $110,000 - $151,300 a year
- Full-time
- Bachelor of Science
- 3 years
- Doctor of Philosophy
- Paid jury duty
- Commuter assistance
Quick Apply
8d

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Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions

General Dynamics Mission Systems, Inc -
Scottsdale, AZ

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Job Details

Full-time
$135,396 - $150,205 a year

Qualifications

Verification (System development task)
Metrics Reporting
Technical report writing
Debugging
Test Planning (Quality assurance practices)

Full Job Description

Basic Qualifications :

Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience.

CLEARANCE REQUIREMENTS: Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Responsibilities for this Position:

What You'll Do

Take ownership, lead, develop and maintain UVM-based and non-UVM-based verification environments for complex FPGA designs including cryptographic engines, protocol interfaces, and system-level integration testbenches
Create comprehensive verification plans with functional coverage models, coverage goals, and closure criteria aligned to design specifications
Implement constrained-random stimulus generators, monitors, scoreboards, and functional coverage collectors using SystemVerilog, VHDL and UVM
Drive code coverage (statement, branch, condition, expression, toggle) and functional coverage to closure, analyzing coverage holes and developing targeted stimulus to fill gaps
Develop and maintain automated simulation regression suites that run across multiple test configurations and random seeds
- including nightly regression runs, coverage trend tracking, and automated results reporting using Jenkins, GitLab CI, or similar platforms
Perform assertion-based verification (ABV) using SystemVerilog Assertions (SVA) to capture protocol rules, interface contracts, and design invariants
Debug complex design issues using waveform analysis (QuestaSim, Vivado), assertion failures, and coverage-driven investigation
Collaborate closely with FPGA design engineers during architecture definition to ensure designs are verification-friendly and observable
Review and contribute to design specifications, interface control documents, and verification closure reports
Mentor junior verification engineers on UVM methodology, coverage-driven verification practices, and debugging techniques
Support formal verification activities including property checking, connectivity verification, and equivalence checking where applicable

Required Qualifications

Strong proficiency in SystemVerilog for verification, VHDL for verification including constrained-random stimulus, functional coverage, and assertions
Hands-on experience with UVM (Universal Verification Methodology) including environment architecture, component development, and sequence libraries
Experience with industry-standard simulation tools: QuestaSim/ModelSim Simulators
Demonstrated ability to develop verification plans, define coverage models, and drive coverage to closure
Experience with code coverage metrics (statement, branch, condition, expression, toggle) and coverage analysis workflows
Proficiency in VHDL and/or Verilog for reading and understanding design RTL
Experience with waveform debugging and signal-level analysis
Understanding of AXI-Stream, AXI4, and similar on-chip bus protocols from a verification perspective
Knowledge of clock domain crossing (CDC) verification concepts and metastability analysis
Strong written and verbal communication skills for verification plans, coverage reports, and technical presentations
S. Citizenship and ability to obtain/maintain a Secret security clearance

Preferred Qualifications

Experience verifying cryptographic hardware implementations (AES, GCM, SHA, ECC, RSA, or similar)
- including automated regression management, seed management, and coverage merging
Proficiency in scripting languages (Python, Tcl, Bash, Perl) for verification automation, log parsing, and results analysis
Experience with Xilinx Vivado Design Suite and FPGA-specific verification challenges (timing simulation, post-synthesis/post-route verification)
Knowledge of CDC analysis tools (Questa CDC) and lint/design rule checking tools
Experience with emulation or prototyping platforms for hardware-in-the-loop verification
Knowledge of AXI protocol specification and Questa verification IP (QVIP) usage for protocol compliance checking
Experience with version control (Git), code review processes, and collaborative development workflows

Salary Note: This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled. Combined Salary Range: USD $135,396.00 - USD $150,205.00 /Yr. Company Overview:

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans

Apply Now

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