Top 26647 Design/verification engineer Jobs

Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions
General Dynamics Mission Systems, Inc —Scottsdale, AZ
- $135,396 - $150,205 a year
- Full-time
- 3 years
- Master's degree
- Analysis skills
Software Engineer - Avionics RF Design and Integration
Capgemini —Atlanta, GA
- $79,750 - $159,500 a year
- Full-time
- Senior level
- Python
- Paid holidays
- Disability insurance
12d
Principal Design Verification Engineer - PCIe / High-Speed SoC
Everforth —Santa Clara, CA
- $200,000 - $250,000 a year
- Full-time
- Management
- Analysis skills
- C++
- Employee stock purchase plan
- Paid holidays
11d
Power Design Engineer
The Judge Group —Rolling Meadows, IL
- $80 - $115 an hour
- Full-time
- Laboratory experience
- Mid-level
- Master's degree
Quick Apply
Digital Design Engineer - Level 5 - Linthicum
Northrop Grumman —Linthicum Heights, MD
- $185,900 - $278,900 a year
- Overtime
- Computer science
- 7 years
- Computer Science
- Paid holidays
- Disability insurance
Video Design Verification Engineer
Qualcomm —San Diego, CA
- $99,400 - $149,200 a year
- Computer Science
- Mid-level
- Master's degree
Design Verification Engineer II
Minnetronix Medical —Saint Paul, MN
- $75,000 - $95,000 a year
- Bachelor of Science
- Data analysis skills
- Laboratory experience
- Dental insurance
- 401(k)
Design Verification Engineer II
Forj Medical —Saint Paul, MN
- $75,000 - $95,000 a year
- Full-time
- Bachelor of Science
- Data analysis skills
- Laboratory experience
- Dental insurance
- 401(k)
Quick Apply
Circuit Design Engineer - New College Grad 2026
NVIDIA —Santa Clara, CA
- $116,000 - $189,750 a year
- Full-time
- Data analysis skills
- Analysis skills
- Software development experience
Sr. Design Verification Engineer
Talent 101 Inc —Dallas, TX
- $0 a year
- Full-time
- Background check
- 18 years or older
- 6 years
Quick Apply
Digital Design Verification Engineer (AZ)
Talent 101 Inc —Tucson, AZ
- $0 a year
- Full-time
- Background check
- 18 years or older
- Pass drug screening
Quick Apply
ASIC Design Verification Engineer
Avicena Tech —Sunnyvale, CA
- $0 a year
- Full-time
- Mid-level
- 3 years
- Master's degree
Quick Apply
Digital Design Engineer
Qualcomm —Santa Clara, CA
- $146,711 - $161,200 a year
- Computer Science
- Mid-level
- Master's degree
Space Mission Requirements and Planning Systems Engineer II (Top Secret / Sensitive Compartmented Information Clearance Required)
Blue Origin —Denver, CO
- $90,934.00 - $138,880.35 a year
- Full-time
- Background check
- Bachelor of Science
- Engineering
- Paid parental leave
- Paid holidays
Entry Level Mechanical Design Engineer
ABCO Subsea, LLC —Houston, TX
- $70,000 - $95,000 a year
- Full-time
- Bachelor of Science
- Engineering
- Data entry
- Paid holidays
- Dental insurance
Quick Apply
Memory Control Design Engineer
Qualcomm —San Diego, CA
- $98,500 - $147,700 a year
- Computer Science
- Engineering
- Mid-level
8d
Production Design Engineer
Pacific Northwest National Laboratory —Richland, WA
- $148,000 - $233,900 a year
- Full-time
- Bachelor of Science
- Pass drug screening
- Mid-level
- Health savings account
- Paid holidays
3d
Design Assurance Engineer II
Abbott Laboratories —Plymouth, MN
- $61,300 - $122,700 a year
- Full-time
- Engineering
- Mid-level
- Office
- Health insurance
- Tuition reimbursement
Test Engineer I - Early Career (2026 Starts)
Blue Origin —Florida
- Background check
- Bachelor of Science
- DOT physical examination
- Paid parental leave
- Paid holidays
Systems Engineer - MBSE Specialist
SOUTHEASTERN COMP CONSULTANTS INC —King George, VA
- Computer science
- Bachelor of Science
- 1 year
- Paid holidays
- Health insurance

I want to receive the latest job alert for design/verification engineer

By signing in to your account, you agree to SimplyHired's Terms of Service and consent to our Cookie and Privacy Policy.

Explore jobs in more locations

design/verification engineer jobs near

Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions

General Dynamics Mission Systems, Inc -
Scottsdale, AZ

Apply Now

Job Details

Full-time
$135,396 - $150,205 a year

Qualifications

Verification (System development task)
Metrics Reporting
Technical report writing
Debugging
Test Planning (Quality assurance practices)

Full Job Description

Basic Qualifications :

Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience.

CLEARANCE REQUIREMENTS: Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Responsibilities for this Position:

What You'll Do

Take ownership, lead, develop and maintain UVM-based and non-UVM-based verification environments for complex FPGA designs including cryptographic engines, protocol interfaces, and system-level integration testbenches
Create comprehensive verification plans with functional coverage models, coverage goals, and closure criteria aligned to design specifications
Implement constrained-random stimulus generators, monitors, scoreboards, and functional coverage collectors using SystemVerilog, VHDL and UVM
Drive code coverage (statement, branch, condition, expression, toggle) and functional coverage to closure, analyzing coverage holes and developing targeted stimulus to fill gaps
Develop and maintain automated simulation regression suites that run across multiple test configurations and random seeds
- including nightly regression runs, coverage trend tracking, and automated results reporting using Jenkins, GitLab CI, or similar platforms
Perform assertion-based verification (ABV) using SystemVerilog Assertions (SVA) to capture protocol rules, interface contracts, and design invariants
Debug complex design issues using waveform analysis (QuestaSim, Vivado), assertion failures, and coverage-driven investigation
Collaborate closely with FPGA design engineers during architecture definition to ensure designs are verification-friendly and observable
Review and contribute to design specifications, interface control documents, and verification closure reports
Mentor junior verification engineers on UVM methodology, coverage-driven verification practices, and debugging techniques
Support formal verification activities including property checking, connectivity verification, and equivalence checking where applicable

Required Qualifications

Strong proficiency in SystemVerilog for verification, VHDL for verification including constrained-random stimulus, functional coverage, and assertions
Hands-on experience with UVM (Universal Verification Methodology) including environment architecture, component development, and sequence libraries
Experience with industry-standard simulation tools: QuestaSim/ModelSim Simulators
Demonstrated ability to develop verification plans, define coverage models, and drive coverage to closure
Experience with code coverage metrics (statement, branch, condition, expression, toggle) and coverage analysis workflows
Proficiency in VHDL and/or Verilog for reading and understanding design RTL
Experience with waveform debugging and signal-level analysis
Understanding of AXI-Stream, AXI4, and similar on-chip bus protocols from a verification perspective
Knowledge of clock domain crossing (CDC) verification concepts and metastability analysis
Strong written and verbal communication skills for verification plans, coverage reports, and technical presentations
S. Citizenship and ability to obtain/maintain a Secret security clearance

Preferred Qualifications

Experience verifying cryptographic hardware implementations (AES, GCM, SHA, ECC, RSA, or similar)
- including automated regression management, seed management, and coverage merging
Proficiency in scripting languages (Python, Tcl, Bash, Perl) for verification automation, log parsing, and results analysis
Experience with Xilinx Vivado Design Suite and FPGA-specific verification challenges (timing simulation, post-synthesis/post-route verification)
Knowledge of CDC analysis tools (Questa CDC) and lint/design rule checking tools
Experience with emulation or prototyping platforms for hardware-in-the-loop verification
Knowledge of AXI protocol specification and Questa verification IP (QVIP) usage for protocol compliance checking
Experience with version control (Git), code review processes, and collaborative development workflows

Salary Note: This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled. Combined Salary Range: USD $135,396.00 - USD $150,205.00 /Yr. Company Overview:

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans

Apply Now

Refine Your Search

design/verification engineer jobs

Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions

Software Engineer - Avionics RF Design and Integration

Principal Design Verification Engineer - PCIe / High-Speed SoC

Power Design Engineer

Digital Design Engineer - Level 5 - Linthicum

Video Design Verification Engineer

Design Verification Engineer II

Design Verification Engineer II

Circuit Design Engineer - New College Grad 2026

Sr. Design Verification Engineer

Digital Design Verification Engineer (AZ)

ASIC Design Verification Engineer

Digital Design Engineer

Space Mission Requirements and Planning Systems Engineer II (Top Secret / Sensitive Compartmented Information Clearance Required)

Entry Level Mechanical Design Engineer

Memory Control Design Engineer

Production Design Engineer

Design Assurance Engineer II

Test Engineer I - Early Career (2026 Starts)

Systems Engineer - MBSE Specialist

I want to receive the latest job alert for design/verification engineer

Related Searches

Explore jobs in more locations

What You'll Do

Required Qualifications

Preferred Qualifications

Job Seeker Tools

Employer Tools

Browse

Stay Connected