Top 1217 Dft design engineer Jobs

Design for Test (DFT) Engineer
Info Way Group —San Francisco Bay Area, CA
- $50 - $60 an hour
- Full-time
- 5 years
- Master's degree
- In-person
Quick Apply
3d
DFT Design Engineer
Cadence Design Systems —Austin, TX
- Full-time
- Mid-level
- Analysis skills
- 2 years
New College Grad - Design Engineer, HBM DFT
Micron —Richardson, TX
- Master's degree
- In-person
- Electrical Engineering
- Employee stock purchase plan
- Paid holidays
DFT Engineer - New College Grad
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- CAD
- Analysis skills
- Mentoring
Design for Test (DFT) Engineer, Principal
Positron AI —Remote
- $200,000 - $350,000 a year
- Full-time
- Remote
- Bachelor of Science
- 11+ years
- Analysis skills
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4d
Product Engineer - Tessent Design for Test (DFT)
Siemens —Wilsonville, OR
- Full-time
- Hybrid work
- Computer Science
- Bachelor of Science
- English
DFT Design Engineer
Intel —Fort Collins, CO
- $105,650 - $149,150 a year
- Full-time
- Hybrid work
- Computer science
- Computer Science
- No experience needed
- Health insurance
4d
Staff Engineer, PCB Layout
Celestica —Austin, TX
- Office
- Travel
- Mentoring
Test Engineer
Schweitzer Engineering Laboratories, Inc. —Pullman, WA
- $84,200 - $170,400 a year
- Full-time
- Bachelor of Science
- Mid-level
- Residential
- Tuition reimbursement
- Employee stock ownership plan
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Test Engineer
Schweitzer Engineering Laboratories, Inc. —Lewiston, ID
- $84,200 - $170,400 a year
- Full-time
- Bachelor of Science
- Mid-level
- Residential
- Tuition reimbursement
- Employee stock ownership plan
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RF Test Development Engineer
Celestica —Maple Grove, MN
- $118,000 - $150,000 a year
- Full-time
- 7 years
- System design
- Office
- Disability insurance
- Health insurance
Sr. Hardware Engineer-North Carolina
Allied Telesis —Cary, NC
- $110,000 - $130,000 a year
- Full-time
- 6 years
- Research
- Mentoring
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Engines Manufacturing Engineer- (All Levels/All Shifts)
Blue Origin —Huntsville, AL
- Extended hours
- Background check
- Bachelor of Science
- DOT physical examination
- Paid parental leave
- Paid holidays
Engineering Laboratory Manager
Tech Talent Link —Kennewick, WA
- $140,000 - $165,000 a year
- Full-time
- Bachelor of Science
- Maintenance
- Analysis skills
- Health savings account
- Relocation assistance
Quick Apply
5d
Lead ASIC DFT Engineer
Cyient —San Jose, CA
- $80 - $85 an hour
- Full-time
- Analysis skills
- Mentoring
- In-person
Quick Apply
Senior Analog/Mixed-Signal Hardware Engineer
AFEX Fire Suppression Systems —Raleigh, NC
- $80,000 - $130,000 a year
- Full-time
- 5 years
- Analysis skills
- In-person
- Health savings account
- Health insurance
Quick Apply
12d
Senior Software Engineer
Digital Force Technologies —San Diego, CA
- $150,000 - $180,000 a year
- Full-time
- 11+ years
- Java
- 8 years
- Free parking
- Health savings account
Quick Apply
Senior Electrical Engineer
AG Growth International Inc. —Lenexa, KS
- Laboratory experience
- Analysis skills
- US work authorization
Verification Engineer
Actalent —New York, NY
- $70 an hour
- Contract
- Mid-level
- Analysis skills
- Continuous improvement
- Commuter assistance
- Health savings account
Quick Apply
10h
Lead Manufacturing Test Engineer (Electrical/Electronics)
Noramtec Consultants Americas —Batesburg, SC
- $100,000 - $125,000 a year
- Full-time
- Background check
- 8 years
- Bachelor's degree
- Health savings account
- Health insurance
Quick Apply

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Design for Test (DFT) Engineer

Info Way Group -
San Francisco Bay Area, CA

Quick Apply

Job Details

Full-time | Contract
$50 - $60 an hour
3 days ago

Qualifications

Teamwork
Master's degree
Verilog
SoC
Digital circuit design
Developing automated testing protocols
Simulation tools
Electrical Engineering
Debugging
Cross-functional communication

Full Job Description

Job Summary

We are seeking an experienced Design for Test (DFT) Engineer to join our semiconductor engineering team in the Bay Area, CA. The ideal candidate will have hands-on experience in DFT implementation, scan insertion, ATPG, MBIST/LBIST, and test architecture for advanced SoC designs. You will collaborate with design, verification, physical design, and manufacturing teams to ensure high-quality, testable silicon for next-generation AI and semiconductor products.

Key Responsibilities

Design, implement, and validate DFT architectures for complex SoCs and ASICs.
Perform Scan Insertion, Scan Compression, and Scan Chain verification.
Generate and debug ATPG (Automatic Test Pattern Generation) patterns to achieve high fault coverage.
Implement and validate MBIST (Memory Built-In Self-Test) and LBIST (Logic Built-In Self-Test) solutions.
Develop and verify DFT logic using industry-standard EDA tools.
Perform DFT verification through simulation, pattern validation, and silicon bring-up support.
Analyze test coverage and optimize DFT implementation for improved manufacturability.
Collaborate with RTL, Physical Design, Verification, and Manufacturing teams throughout the product lifecycle.
Support silicon debug, failure analysis, and production test activities.
Prepare DFT documentation, test plans, and implementation reports.

Required Qualifications

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
5+ years of hands-on experience in Design for Test (DFT).
Strong knowledge of:
Scan Insertion
Scan Compression
ATPG
MBIST/LBIST
JTAG / IEEE 1149.x standards
Experience with one or more of the following tools:
Siemens Tessent
Synopsys TestMAX
Cadence Modus
Strong understanding of digital logic design, RTL (Verilog/SystemVerilog), and ASIC/SoC development flow.
Experience with fault models including stuck-at, transition, and path delay testing.
Familiarity with simulation and verification tools.
Strong debugging, analytical, and problem-solving skills.
Excellent communication and collaboration abilities.

Preferred Qualifications

Experience with AI/ML accelerator or high-performance SoC designs.
Knowledge of semiconductor manufacturing test flows.
Experience with scripting languages such as Python, Perl, or Tcl for DFT automation.
Familiarity with low-power DFT methodologies and IEEE standards.

Preferred Skills

Scan Architecture Design
ATPG Debugging
MBIST/LBIST Integration
DFT Verification
Silicon Bring-up
Fault Coverage Analysis
JTAG Boundary Scan
RTL Debugging
Semiconductor Test Methodologies
Cross-functional Collaboration

Pay: $50.00 - $60.00 per hour

Application Question(s):

5+ years of hands-on experience in Design for Test (DFT) - yes/no?
Experience with one or more of the following tools:

Siemens Tessent
Synopsys TestMAX
Cadence Modus

Work Location: In person

Quick Apply

Refine Your Search

dft design engineer jobs

Design for Test (DFT) Engineer

DFT Design Engineer

New College Grad - Design Engineer, HBM DFT

DFT Engineer - New College Grad

Design for Test (DFT) Engineer, Principal

Product Engineer - Tessent Design for Test (DFT)

DFT Design Engineer

Staff Engineer, PCB Layout

Test Engineer

Test Engineer

RF Test Development Engineer

Sr. Hardware Engineer-North Carolina

Engines Manufacturing Engineer- (All Levels/All Shifts)

Engineering Laboratory Manager

Lead ASIC DFT Engineer

Senior Analog/Mixed-Signal Hardware Engineer

Senior Software Engineer

Senior Electrical Engineer

Verification Engineer

Lead Manufacturing Test Engineer (Electrical/Electronics)

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