Top 1235 Dft design engineer Jobs

Design Engineer
Broadcom —San Jose, CA
- $143,800 - $230,000 a year
- Full-time
- Analysis skills
- Fair chance
- Senior level
- Employee stock purchase plan
- Paid holidays
DFT Engineer
Broadcom —San Jose, CA
- $120,000 - $192,000 a year
- Full-time
- 8 years
- Analysis skills
- Bachelor's degree
- Employee stock purchase plan
- Paid holidays
Hardware Engineer (Digital & Analog Circuit Design)
Savant —Barnstable, MA
- $90,000 - $140,000 a year
- Full-time
- Mid-level
- 3 years
- Master's degree
- Health savings account
- Paid holidays
Quick Apply
Memory Circuit Design Engineer
Broadcom —Mendota Heights, MN
- $91,000 - $146,000 a year
- Full-time
- 5 years
- Bachelor of Science
- Writing skills
- Employee stock purchase plan
- Paid holidays
Electrical Design Engineer
Siemens —Atlanta, GA
- Full-time
- Mid-level
- US work authorization
- 2 years
ASIC DFT STA Engineer
Cisco Systems —San Jose, CA
- $146,700 - $277,600 a year
- Full-time
- Master's degree
- Analysis skills
- Bachelor's degree
- Paid parental leave
- Paid holidays
DFT Design Engineer
Cadence Design Systems —Austin, TX
- Full-time
- Mid-level
- Analysis skills
- 2 years
Digital Design Engineer
Syntiant —San Diego, CA
- $190,000 - $220,000 a year
- Full-time
- English
- Senior level
- Communication skills
- Health savings account
- AD&D insurance
Quick Apply
Digital Design Engineer
Qualcomm —San Diego, CA
- $115,600 - $173,400 a year
- Bachelor of Science
- Engineering
- Mid-level
IC Design Engineer
Broadcom —San Jose, CA
- $143,800 - $230,000 a year
- Full-time
- Master's degree
- Bachelor's degree
- Fair chance
- Employee stock purchase plan
- Paid holidays
ASIC DFT Engineer
Cisco Systems —San Jose, CA
- $135,800 - $252,000 a year
- Full-time
- Hybrid work
- 5 years
- Master's degree
- US work authorization
- Paid parental leave
- Paid holidays
Staff Memory Circuit Design Engineer
Broadcom —Irvine, CA
- $108,000 - $172,800 a year
- Full-time
- Bachelor of Science
- Writing skills
- Data analysis skills
- Employee stock purchase plan
- Paid holidays
Lead ASIC DFT Engineer
ZK Technologies —Remote
- $115,496.06 - $139,092.03 a year
- Contract
- Remote
- Analysis skills
- Mentoring
- Senior level
Quick Apply
DFT Engineer
Select Minds LLC —Santa Clara, CA
- $65 - $130 an hour
- Full-time
- 5 years
- In-person
- Senior level
- Opportunities for advancement
Quick Apply
11d
DFT Engineer - New College Grad
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- CAD
- Analysis skills
- Mentoring
R&D Engineer IC Design 4
Broadcom —San Jose, CA
- $121,900 - $195,000 a year
- Full-time
- 6 years
- Bachelor of Science
- Analysis skills
- Employee stock purchase plan
- Paid holidays
Senior Engineer, Digital Design Engineer
Analog Devices —Wilmington, MA
- $116,960 - $160,820 a year
- Full-time
- 5 years
- Master's degree
- Doctor of Philosophy
- Paid holidays
- Health insurance
10d
PCB Layout Engineer
Keysight Technologies, Inc. —Calabasas, CA
- $114,620 - $191,030 a year
- Full-time
- Remote
- Schematics
- English
- Mid-level
- Health savings account
- Employee stock purchase plan
Memory Circuit Design Engineer-MN Rochester
Broadcom —Rochester, MN
- $109,700 - $175,500 a year
- Full-time
- Bachelor of Science
- Data analysis skills
- 8 years
- Employee stock purchase plan
- Paid holidays
DFT Engineer( Design for Testability)
Intone Networks —San Jose, CA
- Contract
- Computer science
- Computer Science
- Senior level

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Design Engineer

Broadcom -
San Jose, CA

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Job Details

Full-time
$143,800 - $230,000 a year

Benefits

Employee stock purchase plan
Paid holidays
Health insurance
Dental insurance
Family leave
Employee assistance program
Vision insurance
401(k) matching
Paid sick time

Qualifications

Verification (System development task)
Python
Debugging

Full Job Description

Please Note:

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Job Description:

In this position you will use your physical design expertise to do physical implementation of challenging designs in 2nm/3nm/5nm technology nodes . The person should have hands on experience on netlist->gds implementation of multimillion gates including but not limited to floorplanning

place and route, STA, physical verification(LVS?DRC/ANT/ERC). Work closely with designers and must be able to write TCL script to perform custom/semi-custom standard cells placements/clock tree adjustments/routing to achieve design specs. Good timing analysis and CTS knowledge is required. Full chip assembly and experience on spice simulation is a plus.

Job Requirements:

MSEE/MSCS 10+ years (BSEE/BSCS 12+ years)
Expertise in Cadence Innovus/Atop physical design tools
Experience on Calibre LVS/DRC
Work closely with RTL & DFT designers
Strong TCL/Python scripting knowledge required, Perl is a plus.
Good debug skill and be able to work around issues
Tape out experience
must be a good team player

Plus:

Hands on experience on hierarchical top level floorplanning, IO ring design, place and route, clock tree building, STA is preferable.

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $143,800.00 - $230,000.00.

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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Refine Your Search

dft design engineer jobs

Design Engineer

DFT Engineer

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DFT Engineer

DFT Engineer - New College Grad

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DFT Engineer( Design for Testability)

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