Top 1236 Dft design engineer Jobs

Principal Design Verification Engineer
Everforth —San Jose, CA
- Full-time
- Data analysis skills
- Doctor of Philosophy
- Fair chance
- Dental insurance
- 401(k)
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New College Grad - Design Engineer, HBM DFT
Micron —Richardson, TX
- Master's degree
- Electrical Engineering
- Entry level
- Employee stock purchase plan
- Paid holidays
DFT Design Engineer
Cadence Design Systems —Austin, TX
- Full-time
- Mid-level
- Analysis skills
- 2 years
DFT (Design For Test) Engineer
Etched —San Jose, CA
- $150,000 - $275,000 a year
- Full-time
- Data analysis skills
- Research
- Office
- Health insurance
- Dental insurance
DFT Design Engineer I, AWS Machine Learning Acceleration
Annapurna Labs (U.S.) Inc. —Austin, TX
- $104,000 - $185,000 a year
- Full-time
- Mid-level
- Electrical Engineering
- Python
Design for Test (DFT) Engineer, Principal
Positron AI —Remote
- $200,000 - $350,000 a year
- Full-time
- Remote
- Bachelor of Science
- 11+ years
- Analysis skills
Quick Apply
9d
ASIC Clocks Design Engineer - New College Grad 2026
NVIDIA —Austin, TX
- $100,000 - $189,750 a year
- Full-time
- Mid-level
- Electrical Engineering
ASIC Design Engineer - New College Grad 2026
NVIDIA —Santa Clara, CA
- $100,000 - $189,750 a year
- Full-time
- Computer science
- Computer Science
- Bachelor of Science
1d
CPU Circuit Design Engineer
Intel —Austin, TX
- $91,150 - $172,860 a year
- Full-time
- Master's degree
- 1 year
- Electrical Engineering
- Health insurance
DFT Engineer - New College Grad
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- CAD
- Analysis skills
- Mentoring
Design Verification Engineer
Arm —Chandler, AZ
- $130,100 - $176,000 a year
- Email
- Computer Science
- Mid-level
- Electrical Engineering
DFT Engineer
Qualcomm —Santa Clara, CA
- $140,000 - $210,000 a year
- Engineering
- Doctor of Philosophy
- Senior level
Senior Applied AI and AI Infrastructure Engineer - Chip Design and DFX
NVIDIA —Santa Clara, CA
- $200,000 - $379,500 a year
- Full-time
- Azure
- 6 years
- Master's degree
Senior Design Engineer (Remote)
Collins Aerospace —Columbia, SC
- $86,800 - $165,200 a year
- Full-time
- Remote
- 3 years
- Travel
- Mentoring
- Paid holidays
- Loan repayment program
11d
ASIC Design Engineer - Hardware
NVIDIA —Austin, TX
- $116,000 - $218,500 a year
- Full-time
- Hybrid work
- Bachelor of Science
- Mid-level
- Analysis skills
Product Engineer - Tessent Design for Test (DFT)
Siemens —Wilsonville, OR
- Full-time
- Hybrid work
- Computer Science
- Bachelor of Science
- English
DFT Engineer( Design for Testability)
Intone Networks —San Jose, CA
- Contract
- Computer science
- Computer Science
- Senior level
Principal Engineer - Design For Test (DFT)
Marvell —Morrisville, NC
- $160,400 - $237,320 a year
- Full-time
- Computer Science
- Master's degree
- Doctor of Philosophy
- Employee stock purchase plan
Senior ASIC Floorplan Design Engineer
NVIDIA —Austin, TX
- $196,000 - $310,500 a year
- Full-time
- Master's degree
- Continuous improvement
- Senior level
Hardware Design Engineer - Graphics Silicon Implementation
Qualcomm —San Diego, CA
- $161,800 - $242,600 a year
- Computer science
- Computer Science
- Mid-level

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Principal Design Verification Engineer

Everforth -
San Jose, CA

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Job Details

Full-time

Benefits

Dental insurance
401(k)
Vision insurance

Qualifications

Managing projects in an engineering role
Team leadership
Communications systems expertise (engineering specialty)
Electronics design
Managing design projects
Digital circuit design
Design engineering
System architecture design
Managing projects
Simulation tools

Full Job Description

Principal Design Verification Engineer

We are looking for an experienced and passionate Principal Engineer / Manager to join our team. In this role, you will be responsible for hands-on technical work while creating & managing the front-to-back design for our cutting-edge wireless infrastructure SOCs, from architecture and RTL through logic design.

Key Responsibilities:

Create and manage digital designs for SOCs from architecture and RTL to logic design
Utilize tools such as Verification, Mixed Signal, Power Management, Synthesis, static timing, SystemVerilog, ATPG, Fault Grading, SCAN, Clock-domain, BIST, DFM, TCL, Python, Wireless, Amba, Protocol Bus Architecture, DFT, ARM/RISC, AXI/AHB/APB, Multi-core CPU, VHDL/Verilog and Fault Coverage Analysis
Develop and implement strategies to improve the performance of the digital design process
Work with stakeholders to ensure customer satisfaction and customer requirements
Analyze and interpret digital network and system data to identify areas of improvement
Develop and maintain documentation for processes, procedures and design standards
Stay abreast of the latest digital design trends and techniques
Identify areas of risk and take corrective action to mitigate them

Qualifications:

MS / PhD in Electrical Engineering, Computer Engineering or related field

- Wireless communication & protocol experience - i.e. WiFi, 4G/5G, LTE, 3GPP, etc.

Proven experience in digital design, architecture, RTL, and logic design
Hands on experience with AMBA AXI/APB/AHB protocol bus architecture specs & implementations

Verilog, VHDL & System verilog language experience & tools like linting, simulation, formal verification, clock-domain crossing checking, etc.
ARM/RISC architecture, multi-core CPU system memory & operation hierarchy experience
UVM/OVM methodology & language (SystemVerilog) experience
Ability to manage multiple projects with tight deadlines

- Programming & Scripting experience - i.e. C/C++, Tcl, Python, Perl, awk, sed, etc.

Excellent leadership experience & technical capabilities, wear multiple hats
Nice to have skills & tech include: Verification, Mixed Signal, Power Management, Synthesis, static timing, SystemVerilog, ATPG, Fault Grading, SCAN, Clock-domain, BIST, DFM, TCL, Python,

Benefits

Base Pay, Pre-IPO equity, Health, Dental, Vision, 401k

CyberCoders will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.This job was first posted by CyberCoders on 07/19/2026 and applications will be accepted on an ongoing basis until the position is filled or closed.Everforth CyberCoders is proud to be an Equal Opportunity Employer

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter . Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at [email protected] to make arrangements.

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dft design engineer jobs

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