Top 1145 Dft design engineer Jobs

DFT Design Engineer
Cadence Design Systems —Austin, TX
- Full-time
- Mid-level
- Analysis skills
- 2 years
DFT Engineer
Qualcomm —Santa Clara, CA
- $140,000 - $210,000 a year
- Engineering
- Doctor of Philosophy
- Senior level
ASIC Design Engineer
Qualcomm —Santa Clara, CA
- $126,700 - $190,100 a year
- 5 years
- Engineering
- Analysis skills
DFT Engineers
Ambit Semiconductors —Texas
- 5 years
- Master's degree
- Bachelor's degree
Senior Design Engineer
Arm —Austin, TX
- $161,500 - $218,500 a year
- Email
- Computer science
- 7 years
- Computer Science
- Paid time off
- 401(k) matching
Design Engineer
Broadcom —San Jose, CA
- $143,800 - $230,000 a year
- Full-time
- Analysis skills
- Fair chance
- Senior level
- Employee stock purchase plan
- Paid holidays
DFT Engineer
Retym —Austin, TX
- Full-time
- Master's degree
- Analysis skills
- Senior level
DFT Engineer - New College Grad
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- CAD
- Analysis skills
- Mentoring
DFT Engineer
Wipro Limited —Mountain View, CA
- $45,000 - $121,000 a year
- Pass drug screening
- Mid-level
- 3 years
- Disability insurance
- Health insurance
DFT Engineer
Broadcom —Austin, TX
- $129,400 - $207,000 a year
- Full-time
- 8 years
- Fair chance
- Senior level
- Employee stock purchase plan
- Paid holidays
Digital Design Engineer
Qualcomm —San Diego, CA
- $115,600 - $173,400 a year
- Bachelor of Science
- Engineering
- Mid-level
ASIC Clocks Design Engineer - New College Grad 2026
NVIDIA —Austin, TX
- $100,000 - $189,750 a year
- Full-time
- Mid-level
- Electrical Engineering
Design Engineer
Lumilens —San Jose, CA
- Full-time
- Bachelor of Science
- Mid-level
- 3 years
9d
Circuit Design Engineer
Ampere Computing —Durham, NC
- $147,000 - $220,000 a year
- Full-time
- Hybrid work
- No experience needed
- Mid-level
- 3 years
- Paid holidays
- Health insurance
ASIC Design Engineer
Blue Origin —Central, TX
- Full-time
- Background check
- Bachelor of Science
- DOT physical examination
- Paid parental leave
- Paid holidays
DFT Engineer( Design for Testability)
Intone Networks —San Jose, CA
- Contract
- Computer science
- Computer Science
- Senior level
13d
Senior DFT Engineer
NVIDIA —Santa Clara, CA
- $168,000 - $310,500 a year
- Full-time
- Hybrid work
- 5 years
- Master's degree
- Analysis skills
DFT (Design For Test) Engineer
Etched —San Jose, CA
- $150,000 - $275,000 a year
- Full-time
- Data analysis skills
- Research
- Office
- Health insurance
- Dental insurance
ASIC Design Engineer - Hardware
NVIDIA —Austin, TX
- $116,000 - $218,500 a year
- Full-time
- Hybrid work
- Bachelor of Science
- Mid-level
- Analysis skills
Materials Engineer, DFT & MD, Terafab
Tesla —Austin, TX
- Full-time
- Mid-level
- 3 years
- Databases
- Commuter assistance
- Health savings account

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DFT Design Engineer

Cadence Design Systems -
Austin, TX

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Job Details

Full-time

Qualifications

Defect resolution root cause analysis
Engineering development testing
Verification (System development task)
Defect analysis
SoC
Digital circuit design
Design engineering
Developing automated testing protocols
Test analysis
Debugging
Failure analysis

Full Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

US citizenship Required

We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.

Requirements;

Prior 2-10 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
Should possess intimate knowledge of DFT insertion flows
Basic scan chain insertion using synthesis or other software tools
Experience in compression scan insertion, LBIST and other scan technologies
Intimate knowledge of memory build-in self-test (MBIST)
Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals
Debug and Analysis of failures to improve fault coverage
Verification of ATPG testbenches and debugging root cause of simulation mis-compares
Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687
Knowledge of timing analysis and equivalency checks would be added bonus
US citizenship Required
Ability to work in collaborative team environment
Prior experience with Cadence tools and flows is highly desirable
Should be able to finish DFT tasks independently
Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems
Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers
Self-driven and committed individual who can work in a fast-paced project environment

We’re doing work that matters. Help us solve what others can’t.

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