Top 1151 Dft design engineer Jobs

Design for Test (DFT) Engineer
Info Way Group —San Francisco Bay Area, CA
- $50 - $60 an hour
- Full-time
- 5 years
- Master's degree
- In-person
Quick Apply
3d
Design for Test (DFT) Engineer, Principal
Positron AI —Remote
- $200,000 - $350,000 a year
- Full-time
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4d
DFT Design Engineer
Cadence Design Systems —Austin, TX
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New College Grad - Design Engineer, HBM DFT
Micron —Richardson, TX
- Master's degree
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DFT Engineer - New College Grad
NVIDIA —Santa Clara, CA
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Product Engineer - Tessent Design for Test (DFT)
Siemens —Wilsonville, OR
- Full-time
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- Computer Science
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Lead ASIC DFT Engineer
ZK Technologies —Remote
- $115,496.06 - $139,092.03 a year
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DFT Design Engineer
Intel —Fort Collins, CO
- $105,650 - $149,150 a year
- Full-time
- Hybrid work
- Computer science
- Computer Science
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4d
DFT Engineer( Design for Testability)
Intone Networks —San Jose, CA
- Contract
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11d
ASIC Design Verification Engineer
K2 Space —Remote
- $130,000 - $200,000 a year
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- Bachelor of Science
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ASIC Clocks Design Engineer - New College Grad 2026
NVIDIA —Austin, TX
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- Full-time
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DFT (Design For Test) Engineer
Etched —San Jose, CA
- $150,000 - $275,000 a year
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Senior Physical Design Engineer
NVIDIA —Santa Clara, CA
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- Full-time
- Bachelor of Science
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Sr. Application Engineer - Tessent Design for Test (DFT)
Siemens —Fremont, CA
- $293,400 a year
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Electrical Design Engineer
Siemens —Atlanta, GA
- Full-time
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- US work authorization
- 2 years
ASIC Design Engineer - Hardware
NVIDIA —Austin, TX
- $116,000 - $218,500 a year
- Full-time
- Hybrid work
- Bachelor of Science
- Mid-level
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DFT Engineer
Delos Data Inc —Palo Alto, CA
- $160,000 - $230,000 a year
- Full-time
- Remote
- 5 years
- Master's degree
- Analysis skills
- 401(k)
Quick Apply
ASIC Design Engineer
Blue Origin —Central, TX
- Full-time
- Background check
- Bachelor of Science
- DOT physical examination
- Paid parental leave
- Paid holidays
Staff Engineer, PCB Layout
Celestica —Austin, TX
- Office
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- Mentoring
Test Engineer
Schweitzer Engineering Laboratories, Inc. —Pullman, WA
- $84,200 - $170,400 a year
- Full-time
- Bachelor of Science
- Mid-level
- Residential
- Tuition reimbursement
- Employee stock ownership plan
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Design for Test (DFT) Engineer

Info Way Group -
San Francisco Bay Area, CA

Quick Apply

Job Details

Full-time | Contract
$50 - $60 an hour
3 days ago

Qualifications

Teamwork
Master's degree
Verilog
SoC
Digital circuit design
Developing automated testing protocols
Simulation tools
Electrical Engineering
Debugging
Cross-functional communication

Full Job Description

Job Summary

We are seeking an experienced Design for Test (DFT) Engineer to join our semiconductor engineering team in the Bay Area, CA. The ideal candidate will have hands-on experience in DFT implementation, scan insertion, ATPG, MBIST/LBIST, and test architecture for advanced SoC designs. You will collaborate with design, verification, physical design, and manufacturing teams to ensure high-quality, testable silicon for next-generation AI and semiconductor products.

Key Responsibilities

Design, implement, and validate DFT architectures for complex SoCs and ASICs.
Perform Scan Insertion, Scan Compression, and Scan Chain verification.
Generate and debug ATPG (Automatic Test Pattern Generation) patterns to achieve high fault coverage.
Implement and validate MBIST (Memory Built-In Self-Test) and LBIST (Logic Built-In Self-Test) solutions.
Develop and verify DFT logic using industry-standard EDA tools.
Perform DFT verification through simulation, pattern validation, and silicon bring-up support.
Analyze test coverage and optimize DFT implementation for improved manufacturability.
Collaborate with RTL, Physical Design, Verification, and Manufacturing teams throughout the product lifecycle.
Support silicon debug, failure analysis, and production test activities.
Prepare DFT documentation, test plans, and implementation reports.

Required Qualifications

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
5+ years of hands-on experience in Design for Test (DFT).
Strong knowledge of:
Scan Insertion
Scan Compression
ATPG
MBIST/LBIST
JTAG / IEEE 1149.x standards
Experience with one or more of the following tools:
Siemens Tessent
Synopsys TestMAX
Cadence Modus
Strong understanding of digital logic design, RTL (Verilog/SystemVerilog), and ASIC/SoC development flow.
Experience with fault models including stuck-at, transition, and path delay testing.
Familiarity with simulation and verification tools.
Strong debugging, analytical, and problem-solving skills.
Excellent communication and collaboration abilities.

Preferred Qualifications

Experience with AI/ML accelerator or high-performance SoC designs.
Knowledge of semiconductor manufacturing test flows.
Experience with scripting languages such as Python, Perl, or Tcl for DFT automation.
Familiarity with low-power DFT methodologies and IEEE standards.

Preferred Skills

Scan Architecture Design
ATPG Debugging
MBIST/LBIST Integration
DFT Verification
Silicon Bring-up
Fault Coverage Analysis
JTAG Boundary Scan
RTL Debugging
Semiconductor Test Methodologies
Cross-functional Collaboration

Pay: $50.00 - $60.00 per hour

Application Question(s):

5+ years of hands-on experience in Design for Test (DFT) - yes/no?
Experience with one or more of the following tools:

Siemens Tessent
Synopsys TestMAX
Cadence Modus

Work Location: In person

Quick Apply

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dft design engineer jobs

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