Top 986 Dft design for test engineer Jobs

Electrical Schematic/PCB Design Engineer (Semiconductor Test Hardware)
DFW Test Incorporated —Richardson, TX
- $70,000 - $150,000 a year
- Full-time
- ERP systems
- Mid-level
- 3 years
- Paid holidays
- 401(k)
Quick Apply
DFT Design Engineer
Cadence Design Systems —Austin, TX
- Full-time
- Mid-level
- Analysis skills
- 2 years
DFT Engineers
Ambit Semiconductors —Texas
- 5 years
- Master's degree
- Bachelor's degree
DFT Engineer
Broadcom —San Jose, CA
- $120,000 - $192,000 a year
- Full-time
- 8 years
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- Bachelor's degree
- Employee stock purchase plan
- Paid holidays
EE Design & Test Engineer
Apple —San Francisco Bay Area, CA
- $175,000 - $308,500 a year
- 5 years
- Bachelor of Science
- Writing skills
- Employee stock purchase plan
- Health insurance
Design for Test (DFT) Engineer, Principal
Positron AI —Remote
- $200,000 - $350,000 a year
- Full-time
- Remote
- Bachelor of Science
- 11+ years
- Analysis skills
Quick Apply
10d
Sr. Application Engineer - Tessent Design for Test (DFT)
Siemens —San Francisco, CA
- $293,400 a year
- Full-time
- Hybrid work
- Master's degree
- 8 years
- Analysis skills
Digital Design Engineer
Syntiant —San Diego, CA
- $190,000 - $220,000 a year
- Full-time
- English
- Senior level
- Communication skills
- Health savings account
- AD&D insurance
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DFT Engineer
Seer Solutions Inc —California
- $25 - $45 an hour
- Contract
- 5 years
- Analysis skills
- Bachelor's degree
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6d
DFT Engineer - New College Grad
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- CAD
- Analysis skills
- Mentoring
DFT Engineer
Qualcomm —San Diego, CA
- $140,000 - $210,000 a year
- Engineering
- Doctor of Philosophy
- Senior level
Field Application Engineer - Tessent Design for Test (DFT)
Siemens —Santa Clara, CA
- $293,400 a year
- Full-time
- Hybrid work
- Master's degree
- 8 years
- Analysis skills
Product Engineer - Tessent Design for Test (DFT)
Siemens —Wilsonville, OR
- Full-time
- Hybrid work
- Computer Science
- Bachelor of Science
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Lead ASIC DFT Engineer
ZK Technologies —Remote
- $115,496.06 - $139,092.03 a year
- Contract
- Remote
- Analysis skills
- Mentoring
- Senior level
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DFT Engineer( Design for Testability)
Intone Networks —San Jose, CA
- Contract
- Computer science
- Computer Science
- Senior level
DFT Engineer
Select Minds LLC —Santa Clara, CA
- $65 - $130 an hour
- Full-time
- 5 years
- In-person
- Senior level
- Opportunities for advancement
Quick Apply
12d
Hardware Engineer (Digital & Analog Circuit Design)
Savant —Barnstable, MA
- $90,000 - $140,000 a year
- Full-time
- Mid-level
- 3 years
- Master's degree
- Health savings account
- Paid holidays
Quick Apply
Memory Circuit Design Engineer
Broadcom —Mendota Heights, MN
- $91,000 - $146,000 a year
- Full-time
- 5 years
- Bachelor of Science
- Writing skills
- Employee stock purchase plan
- Paid holidays
DFT Engineer (Design for Test)
Selectmindsllc. —Santa Clara, CA
- $65 - $130 an hour
- Contract
- Background check
- 5 years
- In-person
Quick Apply
3d
Electrical Design Engineer
Siemens —Atlanta, GA
- Full-time
- Mid-level
- US work authorization
- 2 years

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Electrical Schematic/PCB Design Engineer (Semiconductor Test Hardware)

DFW Test Incorporated
Richardson, TX

Quick Apply

Job Details

Full-time
$70,000 - $150,000 a year

Benefits

Paid holidays
401(k)
Paid time off
401(k) matching

Qualifications

Version control
Customer communication
CAD file management
Document control experience within engineering industry
Electrical schematic reading and interpretation
Schematic development for electrical drafting
Electrical relays
Following blueprint specifications
Design engineering
Printed circuit board (PCB) layout
Vendor communication
Cable routing
Design of individual components
Electronic component selection

Full Job Description

About the role:

We’re looking for an engineer who can translate customer inputs—Word specs, Excel netlists/BOMs, interface requirements, and legacy drawings—into robust electrical schematics that drive high‑quality PCB designs for semiconductor test hardware (probe, final test load boards, interface/fixture boards, handler interface, and related assemblies). You’ll own schematic capture and collaborate closely with PCB layout, mechanical, test, and manufacturing partners to deliver first‑pass success on fast‑moving customer programs.

What you’ll do:

Own schematic capture from ambiguous or mixed customer inputs; clarify requirements, define architecture, and drive parts selection and library needs.

Create well‑constrained designs that account for ATE realities (signal integrity, crosstalk, leakage, guarding/guard rings, Kelvin connections, relay/mux topologies, pogo/contactor constraints, ESD, thermal).

Partner with PCB layout to enforce design rules for high‑density, high‑pin‑count boards (fan‑out, length/phase matching, differential pairs, controlled impedance, reference plane strategy, return current).

Generate and maintain deliverables: schematics, netlists, constraints, design notes, BOMs, test points, release packages, and ECOs.

Interface with customers (design reviews, DFM/DFT tradeoffs, risk/mitigation plans) and internal cross‑functional teams (ME, Test, Supply Chain, CM).

Shepherd designs through build: fab/assembly bring‑up support, issue triage, corrective actions, and documentation updates.

Continuously improve our libraries, checklists, and design standards for ATE hardware.

Required qualifications:

3–8+ years in electrical design for PCB‑based products; at least 2+ years specifically in semiconductor test hardware or high‑density mixed‑signal boards (probe/final test, load boards, DUT/contactor boards, or similar).

Schematic capture proficiency in multiple CAD environments, including Cadence Allegro/Concept HDL OrCad and Altium Designer (you can interpret and adapt across tools).

Strong grasp of signal integrity and power integrity fundamentals: termination, return paths, reference plane stitching, decoupling strategy, controlled impedance, crosstalk mitigation.

Experience with mixed‑signal and low‑leakage/low‑noise design (sensor or precision analog helpful), switch/mux/relay trees, level shifting, protection, and EMC/ESD practices.

Comfortable reading/creating BOMs, netlists, constraints, and coordinating part selections with the library/CM team (second sources, lifecycles, lead times).

Ability to convert informal customer artifacts (spreadsheets, drawings, legacy PDFs) into a clean, reviewable schematic with clear notes/assumptions.

Excellent documentation, version control, and ECO discipline; clear, concise communication with customers and vendors.

Nice to have:

Background in ATE platforms (e.g., Advantest, Teradyne) and DUT/socket/contactor constraints.

Experience with high‑current power distribution, RF/coax routing basics, or wide‑bandwidth measurement paths.

Familiarity with DFM/DFT for probe and final test: stacking height, planarity, warpage, fiducials, test access, probe card specifics.

Prior work with constraint‑driven flows (rules for length/phase, topology, via budgets) and SI/PI simulation tools (e.g., Sigrity, HyperLynx).

Scripting/automation for CAD (Altium scripts, SKILL, Python) and PLM/ERP integration.

Experience collaborating with overseas layout partners or CMs and doing supplier bring‑up.

What success looks like in 30 days:

You’ve shipped at least one schematic package from customer inputs to layout handoff with zero critical ECOs.

You’ve introduced at least one library or checklist improvement that reduces review time or rework.

You’re the go‑to for translating messy specs into clear, test‑ready schematics.

Compensation & benefits:

Competitive salary with performance bonus; 401(k) with match; paid time off and holidays.

Job Type: Full-time

Pay: $70,000.00 - $150,000.00 per year

Benefits:

401(k)
401(k) matching
Paid time off

Application Question(s):

Do you have at least 3 years of experience in electrical design for PCB-based products, with at least 2 of those years specifically in semiconductor test hardware or high-density mixed-signal boards?
Do you have proficiency with schematic capture in multiple CAD environments, including Cadence Allegro/Concept HDL, OrCad, and Altium Designer?

Work Location: In person

Quick Apply

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