Top 261 Engineering Jobs in Gilroy, Ca

Lead ASIC DFT Engineer
Cyient —San Jose, CA
- $80 - $85 an hour
- Full-time
- Analysis skills
- Mentoring
- In-person
Quick Apply
Static Timing Analysis Engineer
iTechStack Inc. —San Jose, CA
- $100,000 - $150,000 a year
- Full-time
- 3 years
- Master's degree
- Bachelor's degree
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Program/Project Manager - Electronics Management Services
Cybotics System —San Jose, CA
- $87,240.94 - $99,000.00 a year
- Full-time
- Engineering
- English
- Mid-level
- Health insurance
- Flexible spending account
Quick Apply
3d
Regional Sales Manager
Flow Control Group —California
- $115,000 - $160,000 a year
- Full-time
- Engineering
- Mid-level
- Math
- Paid holidays
- Health insurance
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SMT Process Engineer
Cybotics System —San Jose, CA
- $80,000 - $95,000 a year
- Full-time
- Mid-level
- 3 years
- In-person
- Health insurance
- 401(k)
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Manufacturing Engineer
EnPro Industries —Morgan Hill, CA
- $95,000 - $100,000 a year
- Full-time
- Bachelor of Science
- Engineering
- Analysis skills
CAE Engineer
Apple —San Jose, CA
- $149,200 - $297,200 a year
- 6 years
- Engineering
- Data analysis skills
- Employee stock purchase plan
- Health insurance
Hardware System Design Engineer - Apple Vision Pro
Apple —San Jose, CA
- $129,300 - $225,300 a year
- Mid-level
- Master's degree
- Electrical Engineering
- Employee stock purchase plan
- Health insurance
Civil Engineer
YELLOW VEST CONSTRUCTION INC —Gilroy, CA
- $60 an hour
- Part-time
- Construction site
- Mid-level
- Bachelor's degree
- Opportunities for advancement
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Photolithography Process Engineer
Western Digital —San Jose, CA
- $102,500 - $136,600 a year
- Full-time
- Bachelor of Science
- Research
- SQL
- Health savings account
- AD&D insurance
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(USA) Manager, Facilities Maintenance Operations
Walmart —Gilroy, CA
- $117,000 - $234,000 a year
- Full-time
- High school
- Engineering
- Mid-level
- Paid jury duty
- Disability insurance
Hardware System Validation Engineer
Apple —San Jose, CA
- $129,300 - $225,300 a year
- System design
- Laboratory experience
- Mid-level
- Employee stock purchase plan
- Health insurance
STEM Summer Camp Instructor
Mad Science of the Bay Area —Gilroy, CA
- $400 - $700 a week
- Part-time
- Background check
- Current TB test
- Experience working with children
- Mileage reimbursement
- Food provided
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Material Modeling and Simulation Engineer
Apple —San Jose, CA
- $120,900 - $249,000 a year
- 3 years
- Master's degree
- Doctor of Philosophy
- Employee stock purchase plan
- Health insurance
Design Engineer P17
PacSci EMC —Hollister, CA
- $125,160 - $232,440 a year
- 7 years
- Project management
- Organizational skills
3d
Servo Control Engineer
Western Digital —San Jose, CA
- $115,200 - $153,600 a year
- Full-time
- Research
- Mid-level
- Doctor of Philosophy
- Health savings account
- AD&D insurance
Quick Apply
Mechanical Design Engineer
M/A Com Technolgy Solutions —Morgan Hill, CA
- $82,000 - $131,000 a year
- 5 years
- Presentation skills
- Welding
- Health insurance
- Dental insurance
Manufacturing Engineer I
TEKNOVA —Hollister, CA
- $75,000 - $88,000 a year
- Full-time
- Engineering
- Analysis skills
- Communication skills
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Physical Design Engineer, Machine Learning
Apple —San Jose, CA
- $184,700 - $324,800 a year
- Bachelor of Science
- Master's degree
- Bachelor's degree
- Employee stock purchase plan
- Health insurance
Engineering Test Technician 2
MARKI MICROWAVE LLC —Morgan Hill, CA
- $30 - $40 an hour
- Full-time
- Ability to walk for extended periods
- 5 years
- Mid-level
- AD&D insurance
- Paid holidays
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engineering jobs near gilroy, ca

Lead ASIC DFT Engineer

Cyient -
San Jose, CA

Quick Apply

Job Details

Full-time | Contract
$80 - $85 an hour

Qualifications

Analog circuit design
Engineering development testing
Electronics functional testing
Integrated circuits (ICs)
Ramps
Analysis skills
SoC
System architecture design
Simulation tools
Root cause analysis
Test analysis
Python
Debugging
Cross-functional communication

Full Job Description

Title - Lead ASIC DFT Engineer

Location – San Jose, CA.

Duration - Contract

Job Description

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
Act as a technical escalation point for advanced DFT and post-silicon debug issues.
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

Strong hands-on experience in ASIC DFT with end-to-end ownership.
Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
Experience with MBIST implementation and verification; SMS experience preferred.
Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
Proven post-silicon debug and silicon bring-up experience.
Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

MBIST post-silicon validation.
ATPG simulations and fault coverage debug.
DFT RTL, DFD, DFT verification, and IP-level DFT integration.
DFT SDC creation and DFT timing closure support.
Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
TCL/PERL scripting for DFT automation, reporting, and debug.
Experience working across multiple ASIC technology nodes and complex product development cycles.
Familiarity with yield learning, diagnosis, and manufacturing test optimization.

Pay: $80.00 - $85.00 per hour

Work Location: In person

Quick Apply

Refine Your Search

engineering jobs in gilroy, ca

Lead ASIC DFT Engineer

Static Timing Analysis Engineer

Program/Project Manager - Electronics Management Services

Regional Sales Manager

SMT Process Engineer

Manufacturing Engineer

CAE Engineer

Hardware System Design Engineer - Apple Vision Pro

Civil Engineer

Photolithography Process Engineer

(USA) Manager, Facilities Maintenance Operations

Hardware System Validation Engineer

STEM Summer Camp Instructor

Material Modeling and Simulation Engineer

Design Engineer P17

Servo Control Engineer

Mechanical Design Engineer

Manufacturing Engineer I

Physical Design Engineer, Machine Learning

Engineering Test Technician 2

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