Top 257 Fpga emulation engineer Jobs

FPGA Design Engineer
Normal Computing Corporation —New York, NY
- $200,000 - $280,000 a year
- Full-time
- Hybrid work
- C++
- Senior level
- Python
11d
Senior Applications Engineer - Emulation
Siemens —Wilsonville, OR
- $167,200 - $334,400 a year
- Full-time
- Hybrid work
- 5 years
- Bachelor of Science
- Office
Applications Engineer - FPGA Prototyping
Siemens —Pasadena, CA
- $334,400 a year
- Full-time
- Hybrid work
- 5 years
- Bachelor of Science
- Office
Emulation Engineer
Eridu AI —Saratoga, CA
- $185,000 - $250,000 a year
- Full-time
- Hybrid work
- 5 years
- Data analysis skills
- Master's degree
Senior FPGA/Emulation Validation Engineer
Axiado —San Jose, CA
- $80,000 - $200,000 a year
- Full-time
- 5 years
- Bachelor of Science
- Senior level
Quick Apply
Principal Emulation Engineer
Astera Labs —San Jose, CA
- $209,000 - $230,000 a year
- Urgently hiring
- Computer Science
- Software troubleshooting
- System design
Senior FPGA Prototyping Platform Engineer
NVIDIA —Santa Clara, CA
- $168,000 - $310,500 a year
- Full-time
- Management
- 5 years
- Bachelor of Science
Senior Systems Prototyping and Emulation Engineer
NVIDIA —Santa Clara, CA
- $168,000 - $310,500 a year
- Full-time
- 6 years
- Bachelor of Science
- Senior level
ASIC/FPGA Functional Verification Applications Engineer - Boston/Baltimore/Raleigh
Siemens —Baltimore, MD
- $125,300 - $250,600 a year
- Full-time
- Hybrid work
- Computer science
- Computer Science
- Engineering
- Paid parental leave
- Health insurance
Principal Engineer, Emulation
Intel —Austin, TX
- $220,920 - $311,890 a year
- Full-time
- Hybrid work
- Master's degree
- 8 years
- Bachelor's degree
- Health insurance
ASIC Design Verification Engineer
Positron AI —Remote
- $200,000 - $350,000 a year
- Full-time
- Remote
- Master's degree
- 8 years
- Analysis skills
Quick Apply
Senior FPGA Design Verification Engineer
Intuitive Surgical —Sunnyvale, CA
- $152,000 - $257,200 a year
- Day shift
- Machine learning
- Fair chance
- In-person
Senior Principal Electrical Engineer-FPGA Design- Onsite Tucson, AZ
Raytheon —Tucson, AZ
- $132,400 - $251,600 a year
- Full-time
- Budgeting
- In-person
- Senior level
- Paid holidays
- Disability insurance
13d
Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions
General Dynamics Mission Systems, Inc —Scottsdale, AZ
- $135,396 - $150,205 a year
- Full-time
- 3 years
- Master's degree
- Analysis skills
Electrical Engineers II - FPGA Design - Actively Growing Our Engineering Teams!
Raytheon —Tucson, AZ
- $68,900 - $131,100 a year
- Full-time
- Mid-level
- Electrical Engineering
- 2 years
- Paid holidays
- Disability insurance
Senior Electrical Engineer - FPGA Design
Raytheon —Tewksbury, MA
- $86,800 - $165,200 a year
- Full-time
- 5 years
- Mentoring
- Senior level
- Paid holidays
- Disability insurance
13d
Senior FPGA Design Engineer
Raytheon —Tucson, AZ
- $86,800 - $165,200 a year
- Full-time
- 5 years
- Mentoring
- Senior level
- Paid holidays
- Disability insurance
1d
Wireless Systems Engineer
MatchPointe Group —Seattle, WA
- $140,000 - $190,000 a year
- Extended hours
- System design
- Mid-level
- Master's degree
- Commuter assistance
- Health savings account
Quick Apply
Silicon System Validation Engineer
Experis —Sunnyvale, CA
- $50 - $53 an hour
- Contract
- Computer science
- Computer Science
- Writing skills
Quick Apply
23h
Senior Systems and Test Integration Engineer- Hardware DevOps Environment
General Dynamics Mission Systems, Inc —Scottsdale, AZ
- $112,924 - $125,275 a year
- Full-time
- DevOps
- Windows
- 3 years
- Paid parental leave
- Health insurance

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FPGA Design Engineer

Normal Computing Corporation
New York, NY

Apply Now

Job Details

Full-time
$200,000 - $280,000 a year
11 days ago

Qualifications

AI models
Regression testing implementation
Inter-Integrated Circuit (I2C) protocol
Software engineering
Engineering development testing
Electronics functional testing
Tooling
FPGA
Procurement experience
Defect analysis
VHDL
Universal asynchronous receiver-transmitter (UART) protocol
C++
Docker
Model deployment
Computer hardware
System validation
Serial peripheral interface (SPI) protocol
Oscilloscopes
FPGA circuit design
Root cause analysis
Logic analyzers
Implementing machine learning algorithms
DevOps automation
SystemVerilog
Senior level
Vivado
Prototypes
GitLab
Python

Full Job Description

About Normal Computing

Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.

We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.

Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.

The Role

Validating conventional silicon is a solved discipline. Validating silicon that computes with noise is not, and you will be the one who figures out how. As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early software development, and building the test infrastructure for post-silicon bring-up and characterization. Your scope spans the entire FPGA lifecycle: selecting hardware platforms, implementing complex RTL, debugging in the lab, and writing the software that drives it all, working daily with our silicon, EDA, and research teams.

What You'll Own

FPGA Platform Ownership: Lead the selection, procurement, and bring-up of FPGA prototyping platforms (e.g., HAPS, VCU118/VPK180-class boards, or custom hardware) for pre-silicon RTL validation and software development.
RTL Implementation: Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock-domain architectures, CDC bridges, and timing closure on dense designs.
IP Integration: Integrate in-house designs with third-party and vendor IP; serve as the expert on the AMD/Xilinx ecosystem (Vivado IP Integrator, transceivers, memory controllers).
High-Speed Interfaces: Design, implement, and validate high-speed I/O with a focus on PCIe: our accelerators ship as PCIe cards in standard servers.
Post-Silicon Validation: Build FPGA-based "tester" designs for silicon bring-up, device characterization, and automated test environments.
Hardware-Software Stack: Develop the software layer around the hardware: Python/C++ hardware abstraction, register-map generation, and automated build and regression flows.
Lab Debug: Root-cause complex timing and functional issues in real time using ILA/Vivado Analyzer, oscilloscopes, logic analyzers, and BER/eye-diagram characterization of high-speed links.

What Makes You a Great Fit

Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware, ideally in an ASIC prototyping, emulation, or high-growth hardware environment.
Expert-level SystemVerilog and/or VHDL for synthesis, with deep proficiency in Xilinx Vivado (synthesis, place & route, timing closure, IP catalog).
Hands-on experience implementing and debugging PCIe, plus AXI/AHB, SPI, UART, JTAG, and other common interfaces.
Strong Python for automation, test, and build tooling.
Strong board-level bring-up and lab debugging skills on real hardware.
Startup mindset: you work independently, pivot quickly, and run at ambiguous problems that span hardware, software, and physics.

Bonus Points

Verification frameworks like Cocotb, UVM, or OSVVM.
Experience deploying ML models to FPGAs (hls4ml, FINN, or custom NN-to-RTL flows), or building real-time, sub-microsecond signal processing pipelines.
Mixed-signal ASIC exposure: digital front-ends, ADC/DAC interfaces, or analog compute.
SERDES tuning and signal integrity fundamentals.
CI/CD for hardware (GitLab CI, Docker-based build and test).

Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.

Accessibility Accommodations

Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at [email protected].

Privacy Notice

By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

Compensation Range: $200K - $280K

Apply Now

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fpga emulation engineer jobs

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