Top 2797 Interface design architect Jobs

Principal ASIC Architect - Memory Systems & AI Interconnects
Everforth —South Boston, MA
- $200,000 - $300,000 a year
- Full-time
- Computer Science
- System design
- Doctor of Philosophy
- Relocation assistance
- Health insurance
9d
Entry Level Architect
MKA International, Inc. —Liberty Lake, WA
- $65,000 - $90,000 a year
- Full-time
- Clean driving record
- Residential
- Analysis skills
- Health insurance
- Dental insurance
Quick Apply
Internal Architect / Engineer – Data Center Design
Confidential —King of Prussia, PA
- From $125,000 a year
- Full-time
- 5 years
- Master's degree
- Bachelor's degree
- Health insurance
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Functional Architect - D365
New Balance —Brighton, MA
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- Full-time
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- Azure
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Lead Architect
Cox Automotive —Draper, UT
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Mission Architect - Space Communications Systems
Vantor Inc. —Westminster, CO
- $124,000 - $181,500 a year
- Full-time
- 7 years
- Analysis skills
- Senior level
- 401(k) matching
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Autonomy System Architect
Liebherr Mining Equipment Newport News Co. —Newport News, VA
- $121,000 - $148,000 a year
- Online Application
- Bachelor of Science
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- Continuous improvement
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IT Solution Architect (954)
ABC® Supply Co. Inc. —Beloit, WI
- $126,200 - $158,700 a year
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Architect
Cyntergy —Tulsa, OK
- Full-time
- Microsoft Outlook
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- Assembly
Principal, Architect - Healthcare
Stantec —Houston, TX
- Full-time
- 11+ years
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- Master's degree
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Senior Architect - Landmark
Halliburton —Houston, TX
- Full-time
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Senior Hardware Architect
Cherry Bekaert —Columbia, MD
- 8 years
- In-person
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Landscape Designer/Architect
The Pattie Group —Novelty, OH
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- 5 years
- Residential
- Senior level
- Profit sharing
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Software Architect
Liberty Software —Dallas, TX
- Azure
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- System design
- Health savings account
- Paid holidays
Quick Apply
Architecture and Engineering Project Manager
Womer and Associates Inc —Spokane, WA
- $80,000 - $100,000 a year
- Full-time
- Construction site
- Public speaking
- Bachelor's degree
- Health insurance
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Quick Apply
Senior Data Architect - Landmark
Halliburton —Houston, TX
- Full-time
- Azure
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- Office
Command and Control Enclave (C2E) Architect - Staff Engineer Systems Architect
Northrop Grumman —El Segundo, CA
- $177,000 - $265,600 a year
- Overtime
- Bachelor of Science
- 8 years
- Bachelor's degree
- Paid holidays
- Disability insurance
Technical Architect - MBSE/Digital Engineering
CACI —Remote
- $114,600 - $252,100 a year
- Full-time
- Remote
- 7 years
- Computer Science
- ERP systems
- Health insurance
Industrial Architect
Airbus Aerosystems Kinston, Inc —Kinston, NC
- Email
- Microsoft Excel
- Microsoft Outlook
- Bachelor of Science
- Profit sharing
- Paid parental leave
Enterprise Architect, Senior Advisor
Peraton —Herndon, VA
- $135,000 - $216,000 a year
- Azure
- Computer Science
- PMP
- Health savings account
- Paid holidays

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Principal ASIC Architect - Memory Systems & AI Interconnects

Everforth -
South Boston, MA

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Job Details

Full-time
$200,000 - $300,000 a year
9 days ago

Benefits

Visa sponsorship
Relocation assistance
Health insurance
Dental insurance
Vision insurance
401(k) matching
Life insurance

Qualifications

Data caching
SoC
Digital circuit design
Design engineering
ARM

Full Job Description

Principal ASIC Architect - Memory Systems & AI Interconnects

Job Title: Principal ASIC Architect - Memory Systems & AI Interconnects
Job Location: Santa Clara, CA or Boston, MA
Compensation: $200K - $300K plus bonus and equity
Requirements: ASIC Architecture, Memory Subsystems, CXL / NVLink / PCIe / UCIe/ UALink / RDMA, ARM CHI, AI Accelerators

Our company is working on solving the memory wall for AI. We develop memory-to-compute networking solutions for AI infrastructure, with a focus on high-bandwidth optical interconnects for XPU memory expansion.

Position Overview
We are seeking a Principal ASIC Architect to lead architecture and system-level design of memory subsystems and AI interconnects for next-generation AI accelerators and SoCs. The role combines deep expertise in memory systems architecture, interconnect protocols (CXL, NVLink, UALink, RDMA, ARM CHI, UCIe, PCIe), and performance modeling to define high-bandwidth, low-latency solutions that scale across accelerator, host, and memory fabrics. You will partner with product teams, ASIC design, verification, firmware, and system integration to set architectural direction, drive technical tradeoffs, and ensure robust, high-performance solutions for ML hardware and AI workloads.

Key Responsibilities

Define end-to-end memory and interconnect architectures for AI accelerators, including coherent and non-coherent fabrics, memory pooling, and tiered memory hierarchies.
Lead specification and micro-architecture of interfaces and protocols (CXL, NVLink, UALink, RDMA, UCIe, PCIe, ARM CHI) and their integration into SoC designs and AI accelerators.
Develop performance, latency, and bandwidth models and run system-level simulations to evaluate architectural trade-offs and inform design decisions.
Collaborate with RTL, verification, firmware, and physical design teams to translate architecture into implementable hardware blocks and ensure design-for-performance.
Drive cross-functional reviews with product management, systems teams, and external IP partners to align on interfaces, compliance, and interoperability.
Architect solutions for memory subsystems including HBM, DDR, persistent memory, and CXL-attached devices, optimizing for AI/ML workloads and data movement patterns.
Define verification and validation strategies for interconnect and memory subsystems, including test plans for coherence, error handling, flow control, and performance stress tests.
Mentor and lead other architects and engineers, setting best practices, architectural patterns, and documentation for memory and interconnect subsystems.
Keep abreast of industry trends, emerging protocols, and ecosystem developments; represent the company in standards and partner engagements as needed.
Provide technical leadership during silicon bring-up, performance tuning, and system-level debugging to achieve target performance and reliability metrics.

Qualifications

Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science or related field; MS or PhD preferred.
10+ years of experience in ASIC/SoC architecture, with a significant focus on memory systems and interconnects for high-performance computing or AI.
Deep working knowledge of CXL, NVLink, UALink, RDMA, ARM CHI, UCIe, and PCIe protocols and how they are used to build coherent and high-performance systems.
Experience with memory subsystems (HBM, DDR, persistent memory), memory controller architecture, cache coherency and memory consistency models.
Hands-on experience with AI accelerators, ML hardware architectures, dataflow characteristics of ML workloads, and integration of accelerators into SoCs.
Strong background in performance modeling, system-level simulation, and latency/bandwidth analysis.
Familiarity with RTL design concepts, verification methodologies, and silicon bring-up processes; ability to review microarchitecture and RTL for performance implications.
Excellent written and verbal communication skills; proven ability to collaborate across teams and influence technical decisions.
Proven track record of technical leadership, mentoring engineers, and delivering complex ASIC/SoC projects on schedule.

#Enghp

Benefits

Competitive salary commensurate with experience including base salary, performance-based bonus, and early-stage equity grant
Comprehensive benefits including health, dental, vision, and life insurance
Well-equipped, sunny offices in Santa Clara, CA and Boston, MA
Relocation assistance and visa sponsorship
Perks include a daily lunch stipend, 401k match, and more
A collaborative, continuous-learning work environment with smart, dedicated colleagues engaged in developing the next generation of architecture for high-performance computing
For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. This job was first posted by CyberCoders on 07/16/2026 and applications will be accepted on an ongoing basis until the position is filled or closed.Everforth CyberCoders is proud to be an Equal Opportunity Employer

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter . Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at [email protected] to make arrangements.

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interface design architect jobs

Principal ASIC Architect - Memory Systems & AI Interconnects

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