Top 1639 Memory validation engineer Jobs

Principal ASIC Architect - Memory Systems & AI Interconnects
Everforth —South Boston, MA
- $200,000 - $300,000 a year
- Full-time
- Computer Science
- System design
- Doctor of Philosophy
- Relocation assistance
- Health insurance
High Speed Electrical Validation Engineer
Capgemini —Bellevue, WA
- $68,911 - $161,544 a year
- Full-time
- 7 years
- Senior level
- Paid holidays
- Disability insurance
Senior Agentic AI/ML Engineer
General Dynamics Information Technology —Arlington, VA
- $170,000 - $230,000 a year
- Computer science
- Computer Science
- Office
- Paid time off
- 401(k) matching
Senior Agentic AI/ML Engineer
General Dynamics Information Technology —Arlington, VA
- $170,000 - $230,000 a year
- Computer science
- Computer Science
- Office
- Paid time off
- 401(k) matching
Principal Deployment Engineer
Nscale —New York, NY
- $175,000 - $225,000 a year
- System design
- Mentoring
- Senior level
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Hardware Design Validation Engineer - Memory Subsystem
NVIDIA —Santa Clara, CA
- $108,000 - $212,750 a year
- Full-time
- Software troubleshooting
- Bachelor of Science
- Mid-level
Lead Hardware Design Validation Engineer - Memory Subsystem
NVIDIA —Santa Clara, CA
- $168,000 - $322,000 a year
- Full-time
- Master's degree
- Scripting
- Linux
ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning Acceleration
Annapurna Labs (U.S.) Inc. —Austin, TX
- $136,000 - $212,800 a year
- Full-time
- Computer science
- Computer Science
- Mid-level
- AD&D insurance
- Health insurance
Hardware Verification Engineer, Entry Level
Synopsys —Sunnyvale, CA
- $90,000 - $136,000 a year
- Contract
- Computer science
- Computer Science
- Master's degree
Senior High-Speed IO Validation Engineer
NVIDIA —Santa Clara, CA
- $136,000 - $258,750 a year
- Full-time
- Schematics
- Bachelor of Science
- 3 years
SERVER, DDR MEMORY TRAINING VALIDATION ENGINEER
Advanced Micro Devices, Inc —Austin, TX
- Mid-level
- Continuous improvement
- Electrical Engineering
17h
Lead Hardware Design Validation Engineer
NVIDIA —Santa Clara, CA
- $168,000 - $322,000 a year
- Full-time
- Bachelor of Science
- 8 years
- Travel
Principal Software Engineer, E2E Performance and Goodput — CSP Engagements
NVIDIA —Austin, TX
- $272,000 - $431,250 a year
- Full-time
- Computer science
- Computer Science
- Bachelor of Science
3D Memory Chip Architect and Design, Principal Engineer
Qualcomm —Oregon
- $192,000 - $288,000 a year
- Computer science
- Computer Science
- Engineering
1d
Senior Systems Software Engineer, AI Stack and Performance - DGX Station
NVIDIA —Santa Clara, CA
- $224,000 - $356,500 a year
- Full-time
- Computer science
- Computer Science
- Bachelor of Science
New College Grad - Memory Design Engineer, HBM
Micron —Richardson, TX
- CAD
- Master's degree
- Electrical Engineering
- Employee stock purchase plan
- Paid holidays
Memory Component Engineer Hybrid, San Jose, CA
Cisco Systems —San Jose, CA
- $128,200 - $210,500 a year
- Full-time
- Hybrid work
- 5 years
- Bachelor of Science
- Conflict management
- Paid parental leave
- Paid holidays
Senior Memory Subsystem Firmware Engineer
NVIDIA —Santa Clara, CA
- $152,000 - $241,500 a year
- Full-time
- Hybrid work
- Computer science
- Computer Science
- Bachelor of Science
Design Infrastructure Engineer (Standard and Custom Cell Characterization)-HBM
Micron —Richardson, TX
- Master's degree
- Continuous improvement
- Senior level
- Employee stock purchase plan
- Paid holidays
Staff Machine Learning Engineer
Pinterest —San Francisco, CA
- $189,308 - $389,753 a year
- Computer science
- 7 years
- Computer Science

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Principal ASIC Architect - Memory Systems & AI Interconnects

Everforth -
South Boston, MA

Apply Now

Job Details

Full-time
$200,000 - $300,000 a year

Benefits

Visa sponsorship
Relocation assistance
Health insurance
Dental insurance
Vision insurance
401(k) matching
Life insurance

Qualifications

Data caching
Digital circuit design
Design engineering
ARM

Full Job Description

Principal ASIC Architect - Memory Systems & AI Interconnects

Job Title: Principal ASIC Architect - Memory Systems & AI Interconnects
Job Location: Santa Clara, CA or Boston, MA
Compensation: $200K - $300K plus bonus and equity
Requirements: ASIC Architecture, Memory Subsystems, CXL / NVLink / PCIe / UCIe/ UALink / RDMA, ARM CHI, AI Accelerators

Our company is working on solving the memory wall for AI. We develop memory-to-compute networking solutions for AI infrastructure, with a focus on high-bandwidth optical interconnects for XPU memory expansion.

Position Overview
We are seeking a Principal ASIC Architect to lead architecture and system-level design of memory subsystems and AI interconnects for next-generation AI accelerators and SoCs. The role combines deep expertise in memory systems architecture, interconnect protocols (CXL, NVLink, UALink, RDMA, ARM CHI, UCIe, PCIe), and performance modeling to define high-bandwidth, low-latency solutions that scale across accelerator, host, and memory fabrics. You will partner with product teams, ASIC design, verification, firmware, and system integration to set architectural direction, drive technical tradeoffs, and ensure robust, high-performance solutions for ML hardware and AI workloads.

Key Responsibilities

Define end-to-end memory and interconnect architectures for AI accelerators, including coherent and non-coherent fabrics, memory pooling, and tiered memory hierarchies.
Lead specification and micro-architecture of interfaces and protocols (CXL, NVLink, UALink, RDMA, UCIe, PCIe, ARM CHI) and their integration into SoC designs and AI accelerators.
Develop performance, latency, and bandwidth models and run system-level simulations to evaluate architectural trade-offs and inform design decisions.
Collaborate with RTL, verification, firmware, and physical design teams to translate architecture into implementable hardware blocks and ensure design-for-performance.
Drive cross-functional reviews with product management, systems teams, and external IP partners to align on interfaces, compliance, and interoperability.
Architect solutions for memory subsystems including HBM, DDR, persistent memory, and CXL-attached devices, optimizing for AI/ML workloads and data movement patterns.
Define verification and validation strategies for interconnect and memory subsystems, including test plans for coherence, error handling, flow control, and performance stress tests.
Mentor and lead other architects and engineers, setting best practices, architectural patterns, and documentation for memory and interconnect subsystems.
Keep abreast of industry trends, emerging protocols, and ecosystem developments; represent the company in standards and partner engagements as needed.
Provide technical leadership during silicon bring-up, performance tuning, and system-level debugging to achieve target performance and reliability metrics.

Qualifications

Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science or related field; MS or PhD preferred.
10+ years of experience in ASIC/SoC architecture, with a significant focus on memory systems and interconnects for high-performance computing or AI.
Deep working knowledge of CXL, NVLink, UALink, RDMA, ARM CHI, UCIe, and PCIe protocols and how they are used to build coherent and high-performance systems.
Experience with memory subsystems (HBM, DDR, persistent memory), memory controller architecture, cache coherency and memory consistency models.
Hands-on experience with AI accelerators, ML hardware architectures, dataflow characteristics of ML workloads, and integration of accelerators into SoCs.
Strong background in performance modeling, system-level simulation, and latency/bandwidth analysis.
Familiarity with RTL design concepts, verification methodologies, and silicon bring-up processes; ability to review microarchitecture and RTL for performance implications.
Excellent written and verbal communication skills; proven ability to collaborate across teams and influence technical decisions.
Proven track record of technical leadership, mentoring engineers, and delivering complex ASIC/SoC projects on schedule.

#Enghp

Benefits

Competitive salary commensurate with experience including base salary, performance-based bonus, and early-stage equity grant
Comprehensive benefits including health, dental, vision, and life insurance
Well-equipped, sunny offices in Santa Clara, CA and Boston, MA
Relocation assistance and visa sponsorship
Perks include a daily lunch stipend, 401k match, and more
A collaborative, continuous-learning work environment with smart, dedicated colleagues engaged in developing the next generation of architecture for high-performance computing
For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. This job was first posted by CyberCoders on 07/22/2026 and applications will be accepted on an ongoing basis until the position is filled or closed.Everforth CyberCoders is proud to be an Equal Opportunity Employer

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter . Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at [email protected] to make arrangements.

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Refine Your Search

memory validation engineer jobs

Principal ASIC Architect - Memory Systems & AI Interconnects

High Speed Electrical Validation Engineer

Senior Agentic AI/ML Engineer

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Principal Deployment Engineer

Hardware Design Validation Engineer - Memory Subsystem

Lead Hardware Design Validation Engineer - Memory Subsystem

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SERVER, DDR MEMORY TRAINING VALIDATION ENGINEER

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Principal Software Engineer, E2E Performance and Goodput — CSP Engagements

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Senior Systems Software Engineer, AI Stack and Performance - DGX Station

New College Grad - Memory Design Engineer, HBM

Memory Component Engineer Hybrid, San Jose, CA

Senior Memory Subsystem Firmware Engineer

Design Infrastructure Engineer (Standard and Custom Cell Characterization)-HBM

Staff Machine Learning Engineer

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