Top 38 Perl developer rtl Jobs

Staff System Software Engineer, RTL-to-GDS Flow Platform
NVIDIA —Santa Clara, CA
- $184,000 - $356,500 a year
- Full-time
- Computer Science
- System design
- 11+ years
Software Engineer, Hardware Tools and Methodology - New College Grad 2026
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- Hybrid work
- Master's degree
- C++
- Senior level
System Software Engineer, Engineering Workflow Platform
NVIDIA —Santa Clara, CA
- $152,000 - $287,500 a year
- Full-time
- Computer Science
- Bachelor of Science
- Mid-level
Senior Software Engineer, Hardware Tools and Methodology Development
NVIDIA —Santa Clara, CA
- $136,000 - $264,500 a year
- Full-time
- Hybrid work
- Bachelor of Science
- 3 years
- C++
RTL Design and Integration Engineer
Google —Sunnyvale, CA
- $116,000 - $166,000 a year
- Full-time
- Computer science
- Computer Science
- Mid-level
MTS Digital Engineering
Rambus —Morrisville, NC
- $58,000 - $108,000 a year
- Full-time
- Hybrid work
- Bachelor of Science
- Office
- Electrical Engineering
- Employee stock purchase plan
- Health insurance
TPU RTL Design Engineer
Google —Sunnyvale, CA
- $138,000 - $198,000 a year
- Full-time
- Computer science
- Computer Science
- Master's degree
Senior RTL Design Engineer, TPU
Google —Sunnyvale, CA
- $163,000 - $237,000 a year
- Full-time
- Computer science
- Computer Science
- Master's degree
TPU PCIe RTL Design Engineer
Google —Sunnyvale, CA
- $163,000 - $237,000 a year
- Full-time
- Computer science
- Computer Science
- 5 years
EDA Methodology Architect
NVIDIA —Austin, TX
- $168,000 - $310,500 a year
- Full-time
- Hybrid work
- Computer science
- Computer Science
- Bachelor of Science
Design Technology Co-Optimization Engineer
Google —Sunnyvale, CA
- $138,000 - $198,000 a year
- Full-time
- Computer science
- Computer Science
- Research
Principal Emulation Engineer
Marvell —Santa Clara, CA
- $158,600 - $237,600 a year
- Computer Science
- 5 years
- Bachelor of Science
- Employee stock purchase plan
ASIC RTL Design Engineer, Interconnect & Memory Systems
Tesla —Palo Alto, CA
- $128,000 - $312,000 a year
- Full-time
- Computer science
- Computer Science
- 3 years
- Commuter assistance
- Health savings account
Senior Staff Physical Verification CAD engineer
Marvell —Santa Clara, CA
- $127,630 - $191,200 a year
- Full-time
- Computer Science
- Maintenance
- 3 years
- Employee stock purchase plan
TPU RTL Design Engineer, Networking, Inter-Chip Interconnects
Google —Sunnyvale, CA
- $138,000 - $198,000 a year
- Full-time
- Computer science
- Computer Science
- Master's degree
Senior ASIC Design Engineer, Google Cloud
Google —Sunnyvale, CA
- $163,000 - $237,000 a year
- Full-time
- Computer science
- Computer Science
- Master's degree
Physical Design Lead, ASIC
Google —Sunnyvale, CA
- $192,000 - $279,000 a year
- Full-time
- Computer science
- Management
- Computer Science
Senior TPU RTL Design Engineer, Networking, Inter-Chip Interconnects
Google —Sunnyvale, CA
- $163,000 - $237,000 a year
- Full-time
- Computer science
- Computer Science
- 5 years
Senior ASIC Design Engineer, Hardware Compute Group
Amazon.com Services LLC —Sunnyvale, CA
- $183,000 - $247,600 a year
- Full-time
- Master's degree
- Analysis skills
- Doctor of Philosophy
- AD&D insurance
- Health insurance
Silicon Hardware Emulation Engineer, Google Cloud
Google —Sunnyvale, CA
- $138,000 - $198,000 a year
- Full-time
- Computer science
- Computer Science
- Mid-level

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Staff System Software Engineer, RTL-to-GDS Flow Platform

NVIDIA -
Santa Clara, CA

Apply Now

Job Details

Full-time
$184,000 - $356,500 a year

Qualifications

Software engineering
Linux support
JSON
Linux administration
Shell Scripting
Debugging
Production troubleshooting

Full Job Description

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

What does it take to turn chip-design intent into reliable production workflows? Our Engineering Workflow Platform team builds the user-facing infrastructure touchpoints that help NVIDIA engineers create increasingly complex chips. We connect layered configuration, generated design artifacts, EDA tools, distributed jobs, validation checks, and shared project state. We combine workflow-platform architecture with hands-on systems engineering to solve challenges that conventional web-backend and CI/CD platforms do not encounter. Together, we make critical engineering workflows easier to understand, operate, and evolve safely. Ready to help shape the platform behind NVIDIA’s next generation of chips? Come build it with us!

What you'll be doing:

Design the control plane that turns engineering intent and layered configuration into repeatable workflow stages, generated artifacts, tool execution, and validation results.
Create clear models for dependencies, manifests, workflow state, retries, recovery, provenance, and machine-readable status.
Diagnose and prevent production failures involving Linux processes, environment setup, exit codes, shared filesystems, schedulers, partial writes, and stale artifacts.
Modernize established Make, Tcl, Perl, Python, shell, and YAML infrastructure while preserving behavior for active chip projects.
Partner with chip-design teams, EDA experts, and infrastructure engineers to reproduce failures, deliver compatible migrations, and improve workflow observability.

What we need to see:

Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field, or equivalent experience, at least 12 years of relevant software engineering experience.
Production ownership of workflow, build, release, developer-infrastructure, HPC, storage, or engineering-automation systems with multiple stages, dependencies, and generated outputs.
Strong Linux and POSIX fundamentals spanning files, permissions, symbolic links, processes, environment variables, exit codes, logs, and background jobs.
Practical programming experience in Python, C++, Perl, or a comparable language, along with shell scripting and familiarity with Make, YAML, JSON, or related infrastructure.
Experience designing configuration or state models, debugging production failures, and migrating established systems without disrupting active users.

Ways to stand out from the crowd:

Semiconductor-design or EDA workflow experience across RTL, synthesis, place-and-route, timing, signoff, ECO, or design handoffs.
Experience with LSF, Slurm, Grid Engine, shared compute infrastructure, NFS, or another shared filesystem would make an immediate impact.
Deep ownership of build systems, HPC workflows, release infrastructure, storage platforms, or other artifact-centered engineering systems would bring valuable perspective.
Experience creating structured logs, validation results, manifests, provenance records, dashboards, or actionable workflow diagnostics would help us move faster.
Success modernizing legacy Make, Tcl, Perl, Python, or shell infrastructure while maintaining compatibility, rollback, and reproducibility would set a candidate apart.

Detail you can provide in your cover letter

Describe one workflow platform or automation system you owned. What were its stages, inputs, outputs, and persistent state?
Describe a production Linux failure involving a file, process, environment variable, exit code, shared filesystem, or scheduler. What caused it and how did you fix it?
Describe a migration in which old and new behavior had to remain compatible.
Which of Make, Tcl, Perl, Python, shell, LSF, Slurm, and NFS have you used in production? Briefly describe how.

With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our exclusive engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 184,000 USD - 287,500 USD for Level 4, and 224,000 USD - 356,500 USD for Level 5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until July 20, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Apply Now

Refine Your Search

perl developer rtl jobs

Staff System Software Engineer, RTL-to-GDS Flow Platform

Software Engineer, Hardware Tools and Methodology - New College Grad 2026

System Software Engineer, Engineering Workflow Platform

Senior Software Engineer, Hardware Tools and Methodology Development

RTL Design and Integration Engineer

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TPU RTL Design Engineer

Senior RTL Design Engineer, TPU

TPU PCIe RTL Design Engineer

EDA Methodology Architect

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Principal Emulation Engineer

ASIC RTL Design Engineer, Interconnect & Memory Systems

Senior Staff Physical Verification CAD engineer

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Senior ASIC Design Engineer, Google Cloud

Physical Design Lead, ASIC

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Senior ASIC Design Engineer, Hardware Compute Group

Silicon Hardware Emulation Engineer, Google Cloud

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