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Senior Design Engineer
- newArasan Chip Systems
- San Jose, CAProperty (IP) cores for the Electronic Design Community addressing Mobile Storage, ... Our Total IP Solutions include Synthesizable RTL, Analog/Mixed Signal IP, Verification IP,...
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SMTS - FPGA Design Engineer
Altera
- San Jose, CAAs a Senior MTS Design Engineer of the FPGA central engineering team, you will contribute ... to the following: Interfacing with various design groups to ensure successful...
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FPGA Design Engineer 3 4
- newBoeing
- Pleasanton, CAin Pleasanton, CA is seeking a logic design engineer targeting FPGAs for complex ... systems. Engineering activities include design, implementation, and testing of HDL...
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SR Digital Design & Verification Engineer - jm7213
Imaging Sensors
- Palo Alto, CAJM7213 Engineer, Digital Design & Verification Location:Palo Alto, CA Local candidates ... candidate should demonstrate experience with RTL coding in Verilog, verification,...
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RTL Design Engineer
Algotochip
- Sunnyvale, CADesign and specify microprocessor Develop RTL at component level such as AMBA bus ... Design Engineer and SW Developers to support RTL-related issues Desired: MS/PhD Graduates...
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Microprocessor Design Verification Engineer
High Tech Opportunities
- Santa Clara, CA(DV) team. Responsible for pre-silicon RTL verification of a complex low power, high performance design that includes digital and analog cores. Some of the responsibilities...
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Principal Application Engineer , Physical Design
Cadence Design Systems
- San Jose, CAPrincipal Application Engineer , Physical Design Job ID #:7386 Location:San Jose, CA ... but should be familiar with RTL to GDSII design of integrated circuits including...
from Beyond - 5 days agoclose [ x ]Tired of seeing jobs from this company or website?
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SENIOR ASIC DESIGN ENGINEER (CLOCKS)
NVIDIA
- Santa Clara, CASanta Clara Description SENIOR ASIC DESIGN ENGINEER - CLOCKS #1527907 The NVIDIA Clocks ... industry work experience - Experience in RTL design (Verilog), verification and...
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Lead SOC Design Engineer: Ethernet
Ee-recruiters
- Santa Clara, CAfor the architecture specification and RTL design. -Expertise in ARM SOC's Education ... RTL design is required. -Knowledge of ASIC design, chip verification and test, and...
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Senior Physical Design Engineer
Cavium
- San Jose, CAinto our full chip. Work closely with RTL design team in taking their blocks (coded in ... years of physical CAD experience. Physical design knowledge, from netlist handoff to GDS...
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