Top 703 Rtl validation Jobs

RTL Design Engineer
Wipro Limited —Mountain View, CA
- $100,000 - $180,000 a year
- Pass drug screening
- 8 years
- Senior level
- Disability insurance
- Health insurance
ASIC RTL/SoC Design Engineer
TETRAMEM INC —San Jose, CA
- $110,000 - $300,000 a year
- Full-time
- 5 years
- Senior level
- Leadership
Quick Apply
DDRSS Validation Engineer (RTL + Silicon Debug)
Qualcomm —San Diego, CA
- $140,000 - $210,000 a year
- 6 years
- Engineering
- Doctor of Philosophy
12d
RTL Design Engineer (Silicon Engineering)
SpaceX —Irvine, CA
- $125,000 - $195,000 a year
- Extended hours
- Computer science
- Computer Science
- Mid-level
- Paid parental leave
- Employee stock purchase plan
Lead ASIC DFT Engineer
Cyient —San Jose, CA
- $80 - $85 an hour
- Full-time
- Analysis skills
- Mentoring
- In-person
Quick Apply
Senior FPGA / ASIC Design Assurance Engineer
Cyient —Melbourne, FL
- $101,037.27 - $121,679.30 a year
- Full-time
- Background check
- Computer Science
- 8 years
- Health savings account
- Relocation assistance
Quick Apply
4d
FPGA Engineer
Cyient —Melbourne, FL
- $80,000 - $120,000 a year
- Full-time
- Background check
- 5 years
- Master's degree
- Health savings account
- Relocation assistance
Quick Apply
10d
Digital Design Engineer - Level 5 - Linthicum
Northrop Grumman —Linthicum Heights, MD
- $185,900 - $278,900 a year
- Overtime
- Computer science
- 7 years
- Computer Science
- Paid holidays
- Disability insurance
12d
ASIC Verification Engineer (Python/Cocotb)
Oxford Global Resources —Burlingame, CA
- $80 - $90 an hour
- Full-time
- Hybrid work
- In-person
- Senior level
- Python
- Health insurance
- Dental insurance
Quick Apply
Staff Physical Design Engineer ($300-400k pkg)
Everforth —Fort Collins, CO
- $350,000 - $400,000 a year
- Full-time
- Office
- US work authorization
- Fair chance
- Health savings account
- Employee stock purchase plan
Quick Apply
11d
Master Physical Design Engineering Lead (up to $800k pkg)
Everforth —Fort Collins, CO
- Up to $800,000 a year
- Full-time
- No experience needed
- US work authorization
- Scripting
- Health savings account
- Employee stock purchase plan
11d
Senior Electrical Engineer - ASIC/FPGA Verification (Onsite)
Collins Aerospace —Cedar Rapids, IA
- $86,800 - $165,200 a year
- Full-time
- 3 years
- Scripting
- In-person
- Paid holidays
- Loan repayment program
11d
Staff System Software Engineer, RTL-to-GDS Flow Platform
NVIDIA —Santa Clara, CA
- $184,000 - $356,500 a year
- Full-time
- Computer Science
- CAD
- Bachelor of Science
DFT & Post-Silicon Validation
TechBiz Global GmbH —Minneapolis-Saint Paul, MN
- Full-time
- Hybrid work
- Computer Science
- Master's degree
- Analysis skills
Quick Apply
Post-Silicon Validation Engineer
Etched —San Jose, CA
- $160,000 - $260,000 a year
- Full-time
- 7 years
- Master's degree
- Analysis skills
- Health insurance
- Dental insurance
Digital ASIC/FPGA Engineering
spChips —Carlsbad, CA
- Master's degree
- Analysis skills
- Doctor of Philosophy
Staff Silicon Validation Engineer
Rivian —Palo Alto, CA
- Full-time
- Analysis skills
- Linux
- Senior level
Quick Apply
Lead RTL Design Engineer
Efficient Computer —Austin, TX
- $160,000 - $250,000 a year
- 8 years
- Continuous improvement
- Team management
- Paid parental leave
- Parental leave
Quick Apply
Digital Design Engineer (MPU)
BrainChip, Inc. —Laguna Hills, CA
- Hybrid work
- Mid-level
- 3 years
- Python
Quick Apply
Staff RTL Design Engineer
Arm —Austin, TX
- $198,100 - $268,000 a year
- Email
- Bachelor of Science
- Mid-level
- Office

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RTL Design Engineer

Wipro Limited -
Mountain View, CA

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Job Details

$100,000 - $180,000 a year

Benefits

Disability insurance
Health insurance
Dental insurance
Paid time off

Qualifications

8 years
Verilog
System design for system development
SoC
Digital circuit design
Design engineering
Senior level
Design of individual components
Electrical optimization
Python
Debugging
Engineering validation

Full Job Description

Job Description #body.unify div.unify-button-container .unify-apply-now: focus, #body.unify div.unify-button-container .unify-apply-#body.unify div.unify-button-container .unify-apply-now: focus, #body.unify div.unify-button-container .unify-apply-
Job Title: RTL Design Engineer
City: Mountain View
State/Province: California
Posting Start Date: 6/3/26
Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com.

Job Description:
Job Description

Role Purpose

Role Purpose
Digital Design Engineering/RTL Design Services: Architecture and microarchitecture of System on a Chip (“SOC”) subsystems, Intellectual Property Functional Blocks (“IPs”), sub-IPs, modules, and library components Digital design, using System Verilog and/or Verilog RTL, RTL generators (in Python), and/or high-level synthesis (“HLS”). RTL integration of SoC subsystems, IPs, sub-IPs, modules, and library components SoC-level integration Support mapping of RTL on Zebu and HAPS for IP bring up and E2E validation Design for low power and power intent design using Unified Power Format (“UPF”) Constraint development, synthesis, timing closure, and optimization of the design Code quality checks, including but not limited to Linting, Clock Domain Crossing, Reset Domain Crossing Debug and bug fixes

Mandatory Skills: VLSI Physical Place and Route .

Experience: 8-10 Years .

The expected compensation for this role ranges from $100,000 to $180,000 .

Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience. Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.

Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law.

Wipro provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws. Applications from veterans and people with disabilities are explicitly welcome.

Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention.
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Refine Your Search

rtl validation jobs

RTL Design Engineer

ASIC RTL/SoC Design Engineer

DDRSS Validation Engineer (RTL + Silicon Debug)

RTL Design Engineer (Silicon Engineering)

Lead ASIC DFT Engineer

Senior FPGA / ASIC Design Assurance Engineer

FPGA Engineer

Digital Design Engineer - Level 5 - Linthicum

ASIC Verification Engineer (Python/Cocotb)

Staff Physical Design Engineer ($300-400k pkg)

Master Physical Design Engineering Lead (up to $800k pkg)

Senior Electrical Engineer - ASIC/FPGA Verification (Onsite)

Staff System Software Engineer, RTL-to-GDS Flow Platform

DFT & Post-Silicon Validation

Post-Silicon Validation Engineer

Digital ASIC/FPGA Engineering

Staff Silicon Validation Engineer

Lead RTL Design Engineer

Digital Design Engineer (MPU)

Staff RTL Design Engineer

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