Top 626 Rtl validation engineer Jobs

Lead ASIC DFT Engineer
Cyient —Remote
- From $100 an hour
- Full-time
- Remote
- Analysis skills
- Mentoring
- Senior level
Quick Apply
Electrical Engineer
Entegee —Nashua, NH
- $40 - $55 an hour
- Contract
- Background check
- Bachelor's degree
- Travel
- Commuter assistance
- Disability insurance
Quick Apply
Staff Silicon Validation Engineer
Rivian —Palo Alto, CA
- Full-time
- Analysis skills
- Linux
- Senior level
Quick Apply
DFT Engineer - New College Grad
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- CAD
- Analysis skills
- Mentoring
RTL Design Engineer (Silicon Engineering)
SpaceX —Irvine, CA
- $125,000 - $195,000 a year
- Extended hours
- Computer science
- Computer Science
- Mid-level
- Paid parental leave
- Employee stock purchase plan
CPU Microarchitect/RTL Engineer
Apple —Austin, TX
- Bachelor of Science
- Research
- Mid-level
CPU Silicon Validation Engineer
Apple —Santa Clara, CA
- $129,300 - $194,700 a year
- Computer science
- Computer Science
- Bachelor of Science
- Employee stock purchase plan
- Health insurance
RTL Design Engineer
Apple —Beaverton, OR
- Bachelor of Science
- Analysis skills
- Bachelor's degree
ASIC RTL/SoC Design Engineer
TETRAMEM INC —San Jose, CA
- $110,000 - $300,000 a year
- Full-time
- 5 years
- Senior level
- Leadership
Quick Apply
Lead ASIC DFT Engineer
Cyient —San Jose, CA
- $80 - $85 an hour
- Full-time
- Analysis skills
- Mentoring
- In-person
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Senior FPGA / ASIC Design Assurance Engineer
Cyient —Melbourne, FL
- $101,037.27 - $121,679.30 a year
- Full-time
- Background check
- Computer Science
- 8 years
- Health savings account
- Relocation assistance
Quick Apply
3d
FPGA Engineer
Cyient —Melbourne, FL
- $80,000 - $120,000 a year
- Full-time
- Background check
- 5 years
- Master's degree
- Health savings account
- Relocation assistance
Quick Apply
9d
Staff Physical Design Engineer ($300-400k pkg)
Everforth —Fort Collins, CO
- $350,000 - $400,000 a year
- Full-time
- Office
- US work authorization
- Fair chance
- Health savings account
- Employee stock purchase plan
Quick Apply
10d
Senior Electrical Engineer - ASIC/FPGA Verification (Onsite)
Collins Aerospace —Cedar Rapids, IA
- $86,800 - $165,200 a year
- Full-time
- 3 years
- Scripting
- In-person
- Paid holidays
- Loan repayment program
10d
Sr. ASIC RTL Design Engineer
Everforth —Irvine, CA
- $150,000 - $250,000 a year
- Full-time
- 5 years
- Master's degree
- US work authorization
- Health insurance
- Dental insurance
Quick Apply
3d
Master Physical Design Engineering Lead (up to $800k pkg)
Everforth —Fort Collins, CO
- Up to $800,000 a year
- Full-time
- No experience needed
- US work authorization
- Scripting
- Health savings account
- Employee stock purchase plan
10d
Principal Physical Design Engineering Lead ($400-500k)
Everforth —Fort Collins, CO
- Up to $230,000 a year
- Full-time
- No experience needed
- US work authorization
- Scripting
- Health savings account
- Employee stock purchase plan
12d
Emulation and FPGA Prototyping Engineer
GS Microelectronics US Inc. —San Jose, CA
- $150,000 - $250,000 a year
- Full-time
- Computer Science
- 5 years
- Master's degree
- Health insurance
- Dental insurance
Quick Apply
5d
Principal Design Verification Engineer - PCIe / High-Speed SoC
Everforth —Santa Clara, CA
- $200,000 - $250,000 a year
- Full-time
- Management
- Analysis skills
- C++
- Employee stock purchase plan
- Paid holidays
3d
Principal ASIC Architect - Memory Systems & AI Interconnects
Everforth —South Boston, MA
- $200,000 - $300,000 a year
- Full-time
- Computer Science
- System design
- Doctor of Philosophy
- Relocation assistance
- Health insurance
3d

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Lead ASIC DFT Engineer

Cyient -
Remote

Quick Apply

Job Details

Full-time | Contract
From $100 an hour

Qualifications

Engineering development testing
Electronics functional testing
Integrated circuits (ICs)
Analysis skills
SoC
Digital circuit design
Product development
System architecture design
Simulation tools
Test analysis
Python
Debugging
Cross-functional communication

Full Job Description

Experience

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
Act as a technical escalation point for advanced DFT and post-silicon debug issues.
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

Strong hands-on experience in ASIC DFT with end-to-end ownership.
Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
Experience with MBIST implementation and verification; SMS experience preferred.
Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
Proven post-silicon debug and silicon bring-up experience.
Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

MBIST post-silicon validation.
ATPG simulations and fault coverage debug.
DFT RTL, DFD, DFT verification, and IP-level DFT integration.
DFT SDC creation and DFT timing closure support.
Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
TCL/PERL scripting for DFT automation, reporting, and debug.
Experience working across multiple ASIC technology nodes and complex product development cycles.
Familiarity with yield learning, diagnosis, and manufacturing test optimization.

Pay: From $100.00 per hour

Work Location: Remote

Quick Apply

Refine Your Search

rtl validation engineer jobs

Lead ASIC DFT Engineer

Electrical Engineer

Staff Silicon Validation Engineer

DFT Engineer - New College Grad

RTL Design Engineer (Silicon Engineering)

CPU Microarchitect/RTL Engineer

CPU Silicon Validation Engineer

RTL Design Engineer

ASIC RTL/SoC Design Engineer

Lead ASIC DFT Engineer

Senior FPGA / ASIC Design Assurance Engineer

FPGA Engineer

Staff Physical Design Engineer ($300-400k pkg)

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Sr. ASIC RTL Design Engineer

Master Physical Design Engineering Lead (up to $800k pkg)

Principal Physical Design Engineering Lead ($400-500k)

Emulation and FPGA Prototyping Engineer

Principal Design Verification Engineer - PCIe / High-Speed SoC

Principal ASIC Architect - Memory Systems & AI Interconnects

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