Top 624 Silicon validation architect Jobs

Silicon Architect
Normal Computing Corporation —New York, NY
- $234,001 - $298,252 a year
- Full-time
- Computer science
- Computer Science
- C++
Pre and Post Silicon Validation Engineer
Insilico —San Diego, CA
- Contract
- Software troubleshooting
- Mid-level
- 3 years
Quick Apply
SoC Management Subsystem Architect
Majestic Labs —Los Altos, CA
- Full-time
- 6 years
- System design
- Master's degree
Quick Apply
CPU Performance Architect
Intel —Austin, TX
- $141,910 - $232,190 a year
- Full-time
- Hybrid work
- Computer science
- Computer Science
- Master's degree
- Health insurance
Senior CPU Performance Architect
Intel —Austin, TX
- $190,610 - $361,480 a year
- Full-time
- Hybrid work
- 6 years
- Master's degree
- Analysis skills
- Health insurance
Senior SoC Compute/Memory Subsystem Architect
Intel —Santa Clara, CA
- $164,470 - $269,100 a year
- Full-time
- Hybrid work
- 7 years
- System design
- Office
- Health insurance
Senior Out-of-Order CPU Architect
Intel —Austin, TX
- $190,610 - $361,480 a year
- Full-time
- Hybrid work
- Analysis skills
- Senior level
- Leadership
- Health insurance
Senior Compute Kernel Architect, GPU Power
NVIDIA —Santa Clara, CA
- $184,000 - $356,500 a year
- Full-time
- Computer science
- Computer Science
- 5 years
SOC Architect
OpenAI —San Francisco, CA
- $266,000 - $445,000 a year
- Full-time
- Fair chance
- Senior level
- Communication skills
Principal Silicon Performance Architect
Microsoft —Redmond, WA
- $165,600 - $331,200 a year
- Full-time
- Background check
- Computer Science
- Master's degree
Principal ASIC Architect - Memory Systems & AI Interconnects
Everforth —South Boston, MA
- $200,000 - $300,000 a year
- Full-time
- Computer Science
- System design
- Doctor of Philosophy
- Relocation assistance
- Health insurance
8d
Sr. Principal Hardware Architect
The Hiring Method, LLC —Fremont, CA
- $150,000 - $190,000 a year
- Master's degree
- Analysis skills
- Continuous improvement
- Health insurance
- Dental insurance
Quick Apply
7d
Principal Design Verification Engineer - PCIe / High-Speed SoC
Everforth —Santa Clara, CA
- $200,000 - $250,000 a year
- Full-time
- Management
- Analysis skills
- C++
- Employee stock purchase plan
- Paid holidays
8d
Sr. Software Engineer - AI Compiler & Runtime Infrastructure
Everforth —Irvine, CA
- $190,000 - $260,000 a year
- Full-time
- Hybrid work
- 7 years
- Computer Science
- Master's degree
- Health insurance
- Dental insurance
8d
Senior FPGA Engineer
Everforth —Tempe, AZ
- Full-time
- 5 years
- Master's degree
- Mentoring
- Health insurance
- Dental insurance
Quick Apply
11h
Principal DRAM Architect – GPU Memory Solutions
NVIDIA —Santa Clara, CA
- $272,000 - $431,250 a year
- Full-time
- Hybrid work
- System design
- 11+ years
- Doctor of Philosophy
Senior SoC Chiplet Architect
Intel —Santa Clara, CA
- $164,470 - $269,100 a year
- Full-time
- Hybrid work
- 7 years
- Office
- Telemetry
- Health insurance
Optical System Architect
Ciena —New Providence, NJ
- $117,800 - $188,200 a year
- Full-time
- Data analysis skills
- Master's degree
- Analysis skills
- Employee stock purchase plan
- Paid holidays
HSIO Validation Lead
NVIDIA —Santa Clara, CA
- $168,000 - $310,500 a year
- Full-time
- Hybrid work
- Bachelor of Science
- 8 years
- Senior level
GPU System and Scheduling Architect - New College Grad 2026
NVIDIA —Santa Clara, CA
- $108,000 - $195,500 a year
- Full-time
- Computer Science
- Bachelor of Science
- System design

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Silicon Architect

Normal Computing Corporation
New York, NY

Apply Now

Job Details

Full-time
$234,001 - $298,252 a year

Qualifications

Computer science
Computational research
Computer Science
FPGA
Quantization
Computational modeling
Verilog
System design for system development
C++
Digital circuit design
Doctor of Philosophy
Computer hardware
System validation
Design engineering
Prototype creation
Computer Engineering
Simulation tools
Senior level
Electrical Engineering
Design of individual components
Prototypes
Python
Validation design

Full Job Description

About Normal Computing

Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.

We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.

Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.

The Role

Most accelerator architecture is refinement: a known substrate, a known programming model, decades of prior art to lean on. This seat is not that. Normal's silicon computes with stochastic analog dynamics in memory, and the architecture that exploits it is being discovered alongside the work.

As our Silicon Architect, you will own the architecture of its compute blocks: the core decisions that determine how Normal's silicon actually computes, working directly with our Systems Architect, research and engineering leadership, and the AI platform team whose tools you'll use to design it. This is a seat for someone who wants to define structures no prior art covers, and who has the architecture-to-silicon range to defend them all the way to tapeout.

What You'll Own

Compute Architecture: Help define the architecture and microarchitecture of novel AI accelerator compute blocks: PE array design, datapath organization, and support for efficiency techniques such as sparsity exploitation and reduced-precision computation. The compute tile is the surface where Normal's research advantages have to show up in silicon, and you are one of the people responsible for making sure they do.
Workload-to-Hardware Translation: Translate workload analysis and research findings into hardware specifications. Identify where architectural innovation creates the most leverage, define the structures that realize it, and produce microarchitecture documents unambiguous enough for RTL engineers to implement against. You work closely with them through implementation, not over the wall from it.
Full-Stack PPA Tradeoffs: Reason across the full stack and defend PPA tradeoffs at every level. Move between algorithm-level workload behavior, memory hierarchy, on-chip interconnect, and physical design constraints. Make the call when the data is incomplete, and articulate why under scrutiny from our Systems Architect and the research team.
ISA Co-Design: Partner with the compiler lead on ISA co-design. The compute tile must be compilable and programmable, not just simulatable. The programming model and the microarchitecture are defined together, and you are accountable for both sides meeting in the middle.
Prototyping Strategy: Direct block-level pre-silicon validation. Decide which microarchitecture questions are answered in FPGA versus cycle-accurate simulation, define what each prototype must prove, and partner with our FPGA Design Engineer, who owns implementation and bring-up, to de-risk decisions before tapeout. System-level validation is owned by our Systems Architect.
Research Fluency: Stay current with the AI accelerator research landscape and be able to articulate clearly where Normal's approach differs from existing solutions and why that matters. This is a research-adjacent seat and you are expected to read, not just consume.

What Makes You a Great Fit

A degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience. PhD welcome but not required; the bar is the work, not the credential.
Substantial experience in architecture or microarchitecture of high-performance digital systems: AI accelerators, compute engines, or similarly complex logic. You have shaped the structures inside a chip, not just consumed them from the outside.
Fluency moving between algorithm-level analysis and hardware specification. You can read a profile of a workload and translate it into datapath widths, pipeline stages, and area/power estimates without losing the thread on either side.
Experience with simulation-driven architecture. You have used cycle-accurate or analytical models to make and defend design decisions before RTL exists, and you know which questions each tool can answer and which it cannot.
Familiarity with quantization and reduced-precision approaches for inference and their implementation implications. You understand the cost of a bit at the hardware level, not just the model level.
Experience writing microarchitecture specifications and working closely with RTL engineers through implementation. Your specs are read, not just filed.
Proficiency in Python or C++ for performance modeling and analysis, and familiarity with SystemVerilog or equivalent RTL.
Comfort operating in an environment where the architecture is actively being discovered alongside the work. You do not need the answer to be already known to make progress on it.

Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.

Accessibility Accommodations

Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at [email protected].

Privacy Notice

By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

Compensation Range: $234,001 - $298,252

Apply Now

Refine Your Search

silicon validation architect jobs

Silicon Architect

Pre and Post Silicon Validation Engineer

SoC Management Subsystem Architect

CPU Performance Architect

Senior CPU Performance Architect

Senior SoC Compute/Memory Subsystem Architect

Senior Out-of-Order CPU Architect

Senior Compute Kernel Architect, GPU Power

SOC Architect

Principal Silicon Performance Architect

Principal ASIC Architect - Memory Systems & AI Interconnects

Sr. Principal Hardware Architect

Principal Design Verification Engineer - PCIe / High-Speed SoC

Sr. Software Engineer - AI Compiler & Runtime Infrastructure

Senior FPGA Engineer

Principal DRAM Architect – GPU Memory Solutions

Senior SoC Chiplet Architect

Optical System Architect

HSIO Validation Lead

GPU System and Scheduling Architect - New College Grad 2026

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