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Principal ASIC Development Engineer
- newMicrosemi
- San Jose, CANumber of Positions: 1 Positions Filled: 0 Position Title: Principal ASIC Development Engineer Requisition #: 1762 Country: United States State: California City / Town: San Jose...
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Microprocessor Design Verification Engineer
High Tech Opportunities
- Santa Clara, CASome of the responsibilities include but not limited to testbench/testplans development, block level verification, full-chip verification, coverage driven verification, system &...
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Sr. Staff ASIC Development Engineer
- newMicrosemi
- San Jose, CANumber of Positions: 1 Positions Filled: 0 Position Title: Sr. Staff ASIC Development Engineer Requisition #: 1764 Country: United States State: California City / Town: San Jose...
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Lead SOC Design Engineer: Ethernet
Ee-recruiters
- Santa Clara, CAJoin the leader in Innovation! We are looking for a Lead SOC Engineer to lead our front end team. Responsibilities: -Responsible for the architecture specification and RTL design.
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ASIC Verification Engineer
- newYoh
- Santa Clara, CAthe verification flow and methodology, testbench and test cases, plus executing the test plan, working closely with the design team to ensure the highest design quality. Debug...
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Lead SOC Design Engineer
Ee-recruiters
- Santa Clara, CAJoin the leader in Innovation! We are looking for a Lead SOC Engineer to lead our front end team. Responsibilities: -Responsible for the architecture specification and RTL design.
from Bright.com - 19 days agoclose [ x ]Tired of seeing jobs from this company or website?
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ASIC Design Eng 4
GB Resources
- Santa Clara, CAThe ideal candidate should have 2+ years of CPU verification experience.\n.In-depth knowledge of digital logic design, CPU, debug feature, Power management, and DFT architecture...
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SOC Design Engineers (2)
Ee-recruiters
- Santa Clara, CAJoin the leader in Innovation! We are looking for 10 Senior Engineers to expand our front end team Responsibilities: -Responsible for the architecture specification and RTL design...
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Wireless Modem Hardware Engineer
Private Practice
- Santa Clara, CAmicro architecture, test planning, testbench development, and RTL design, with ... is required. Knowledge of HVLs, OOP, Testbench Architectures, is desirable.
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Sr Applications Engineer - SJ-7594
- newCadence Design Systems
- San Jose, CAeducation or experience in AMBA; Ethernet; Testbench development for block and system level verification; SystemVerilog; Vera; OVM; and C++. Any suitable combination of education,...
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