ASIC Verification Engineer Salaries in Mountain View, CA

Understand the design and implementation of your unit, define the verification scope, develop the verification infrastructure and verify the correctness of the…

$136,000 - $264,500 a year

Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB), and methodologies (UVM or equivalent).

$116,000 - $218,500 a year

Exposure to design and verification tools (VCS or equivalent simulator tools; debug tools like Verdi, Debussy, GDB). Expertise in System Verilog and Verilog.

$100,000 - $189,750 a year

9 days ago

You will also identify improvements in the current design and propose and implement new ways to improve the efficiency in the GPU clocking design.

$116,000 - $218,500 a year

Understand the design and implementation of your unit, define the verification scope, develop the verification infrastructure, and verify the correctness of the…

$168,000 - $310,500 a year

Formal Verification: Utilize formal verification techniques to prove correctness for critical design properties, such as clock domain crossing (CDC) and complex…

$0 a year