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SECRET Lead Digital/FPGA Design EngineerGeneral Dynamics Information Technology - Scottsdale, AZU.S. Federal Security Clearance Requirement: Clearance Required // General Dynamics Information Technology Lead Digital/FPGA Design Engineer JN: RUSAGDES349-641873 Support of digital and FPGA design and development activities for devices to be utilized in hi-reliability spaced-based communications systems. Design and developement responsibilities include all phases of device design, development, and documentation tasks to include concept development, requirements, verification plan, chip architecture, detail RTL or VHDL design, simulation, timing analysis, synthesis, and ATPG. Other tasks include monitoring and providing support for the integration and testing of devices within higher level assembly applications. Candidate must be able to effectively and efficiently work with other team members...originally from DefenseCareers.com - More Tools...
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