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Principal ASIC Verification Engineer - new
Our Design Verification team is growing and has need of a top talent, senior to principal level, ASIC functional verification engineer. Responsible for the development of leading edge verification methodologies and their timely and successful deployment against innovative industry leading, coherent detection, OTN chip solutions at line rates of 100GHz and beyond. Required Skills & Experience Pseudo-random, functional coverage verification methodologies SystemVerilog and SystemVerilog class libraries such as UVM, OVM or VMM Desired Skills Framer experience with SONET or OTN Networking domain knowledge (e.g. Ethernet, ATM, SONET, GFP, OTN) SVA, PSL or OVL assertions SystemC or C++ experience Formal model checking tools (e.g. Cadence IFV, Jasper) DSP is a plus Y...
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