1 - 10 of 40

sta lead engineer jobs near San Jose, CA

  • Staff Design Engineer - Palladium Advanced Product Development

    Cadence Design Systems

    - San Jose, CA

    The Staff Design Engineer will work with Chip, System and Software architects to define ... in running simulation, synthesis, DFT, and STA all advantageous * Experience with...

    17 days ago from Cadence Design Systems, Inc
  • Principal Application Engineer

    Cadence Design Systems

    - San Jose, CA

    As a Principal Application Engineer at Cadence, you will consult with customers on ... Experience with ASIC synthesis and STA * Knowledge and understanding of VHDL...

    30+ days ago from Cadence Design Systems, Inc
  • Sr Applications Engineer

    Cadence Design Systems

    - San Jose, CA

    (Verilog) * Senior Level Applications Engineer position with Deep Cadence or ... Mobile Customers * Senior level Application Engineer position supporting RTL-to-GDS...

    30+ days ago from Cadence Design Systems, Inc
  • Need STA engineer @

    Simplion Technologies

    - San Jose, CA

    Role: STA engineer(Static Timing Analysis Contractor)Location : San Jose, CADuration :6-9 ... fully automated STA scripts/flows using STA tools like Primetime or Nanotime or...

    14 days ago from Simplion Technologies
  • Staff Design Engineer

    NEW

    Xilinx

    - San Jose, CA

    include, architecture, design, STA timing closure, noise and electrical ... tools. * Very good knowledge in STA, Timing Model, STA based timing closure,...

    1 day ago from Xilinx Inc
  • Engineer - IC Design (FPGA)

    NEW

    Broadcom

    - Santa Clara, CA

    Auto req ID 31638BR Job Posting Title Engineer - IC Design (FPGA)* Business Unit Mobile ... Clocks, DCM, MMCM & special I/Os), static timing analysis (STA) o Experience with HAPS and...

    2 hours ago from Broadcom
  • High Performance ARM Principal Physical Design Engineer

    Broadcom

    - Santa Clara, CA

    Performance ARM Principal Physical Design Engineer Business Unit Infrastructure and ... simulation, timing closure(STA), equivalency check, P&R, power estimation, DFT,...

    11 days ago from Broadcom
  • Design Automation Engineer

    Intel

    - San Jose, CA

    layout closure, UPF based power methodology, STA etc. Ability to multi-task and flexibility to work in global environment Good in communication skills and strong motivation for...

    16 days ago from Intel Corporation
  • Technical Lead

    NEW

    Lighthouse Global Resources

    - San Jose, CA

    & Power Delivery Technical Lead San Francisco Bay Area Posted 9 days ... Area Posted 24 days ago * Technical Lead, Full-stack San Francisco Bay Area Posted...

    1 day ago from LinkedIn Corporation
  • Senior level IC Design Engineer (Low Power)

    NEW

    Broadcom

    - Sunnyvale, CA

    IC Design Engineer San Francisco Bay Area Posted 24 days ago * Lead Scientist Power Man ... IC Design Engineer San Francisco Bay Area Posted 24 days ago * Lead Scientist Power…...

    12 hours ago from LinkedIn Corporation
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