ProMedia is hiring engineers to be part of our team supporting a global technology development client based in San Diego.
THIS JOB DOES NOT ALLOW SUBCONTRACTING OR CORP TO CORP ARRANGEMENTS
Scope of Assignment:
Design, implement, verify and tapeout process test structures and circuits in advanced sub-10nm nodes to enable process technology team early electrical target definition, device characterization and optimization, and early yield learning.
- 5+ years minimum layout design experience in sub-20nm CMOS commercial technologies.
- Must have tool experience using 1) Cadence design suite of tools 5.1.4*, 6.1.*, ic12 (layout+schematic) 2) Calibre verification suite (DRC, LVS, ERC, LPE, Softcheck) 3) Design Management tools using Synchronicity's DesignSync 4) UNIX and script automation.
- Must have relevant test structure design, implementation, verification, assembly and tapeout experience on product testlines.
- Test structures include, but not limited to, resistors, capacitors, MOSFETs, ring oscillators, matched circuits.
- Able to capture, design, develop and implement process technology test structures and circuits that allow easy re-use, with consistency across various layout styles that allow flexible updates with minimal effort.
- Ensure layout compliance to Design-Of-Experiment (DOE) documentation and intent.
- Work with process team device and module owners to translate DOE documentation to functional error-free layouts with minimal supervision.
- Knowledgeable in layout dependent and parasitic effects.
- Multi-patterning, finfet technology familiarity required.
- Independently perform dataprep operations like dummy fill, multi-pattern coloring.
- Independently debug Calibre verification results with corrections either to layout or schematic in a timely fashion.
- Must be physically present and available on-site in San Diego campus 5 days a week, 8 hours a day.
- Experience with foundry technology, internal tools and Microsoft Excel usage a plus.
- Good knowledge of analog sensitive/critical circuits (matching, symmetry, parasitic IR drop identification).
- Experience with foundry Cadence techfile, map file setup, ability to use foundry supplied verification decks using Calibre Interactive highly desirable.
- Able to write concise daily progress reports on goals.
- Preferred: Bachelor's, Electrical Engineering or equivalent experience.