Technologist, ASIC Development Engineering

Western Digital - Milpitas, CA3.8

Full-timeEstimated: $87,000 - $110,000 a year
BSEE or MSEE with a thorough understanding of ASIC implementation and development, with minimum 12 + years of experience

Project/Team Lead experience with multiple tapeouts (28, 16nm) is a must
Extensive knowledge and experience in all aspects of ASIC/SoC designs including synthesis, CDC, constraint generation, timing closure, equivalence and power use.
Deep Knowledge in physical aware synthesis flows, low power flows including multi-Vt, multi-voltage synthesis & power gating insertion (UPF/CPF) in complex SOC's
Hands on experience in full chip Timing Constraints for a complex, multi-clock, multi-voltage SoC including : integration of complex IP constraints ( PCIe, SAS, DDR3, ARM, Source Synchronous Interfaces, etc.,), constraints partitioning (from chip level to block level), IO timing budgeting and overall SDC generation
Experience in running STA analysis and achieving timing closure on multiple high-performance, low power designs
Hands on knowledge and experience on DFT, floor planning, place and route
Experience in working with high speed interfaces in ASIC: DDR, PCIe and/or SAS
RTL design and coding skills ( Verilog/ System Verilog) ( Integration activities) with debugging skills
Understanding and ability to support all backend ASIC activities including Test, Packaging, Characterization, Qual and Reliability
Experience in developing and supporting a fully automated scripts/flows;
Proficient in industry standard EDA tools
Knowledgeable in Power aware functional verification, formal verification and scripting languages (Tcl, Make & Perl)
Capable of coordinating, managing schedule deliverables, reporting status and overseeing tasks execution
Excellent problem solving, verbal and written communication skills